drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
Extension
.c
Size
12269 bytes
Lines
377
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
#include "nv20.h"
#include "regs.h"

#include <core/client.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
#include <subdev/fb.h>
#include <subdev/timer.h>

/*******************************************************************************
 * PGRAPH context
 ******************************************************************************/

int
nv20_gr_chan_init(struct nvkm_object *object)
{
	struct nv20_gr_chan *chan = nv20_gr_chan(object);
	struct nv20_gr *gr = chan->gr;
	u32 inst = nvkm_memory_addr(chan->inst);

	nvkm_kmap(gr->ctxtab);
	nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4);
	nvkm_done(gr->ctxtab);
	return 0;
}

int
nv20_gr_chan_fini(struct nvkm_object *object, enum nvkm_suspend_state suspend)
{
	struct nv20_gr_chan *chan = nv20_gr_chan(object);
	struct nv20_gr *gr = chan->gr;
	struct nvkm_device *device = gr->base.engine.subdev.device;
	u32 inst = nvkm_memory_addr(chan->inst);
	int chid = -1;

	nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
	if (nvkm_rd32(device, 0x400144) & 0x00010000)
		chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
	if (chan->chid == chid) {
		nvkm_wr32(device, 0x400784, inst >> 4);
		nvkm_wr32(device, 0x400788, 0x00000002);
		nvkm_msec(device, 2000,
			if (!nvkm_rd32(device, 0x400700))
				break;
		);
		nvkm_wr32(device, 0x400144, 0x10000000);
		nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);
	}
	nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);

	nvkm_kmap(gr->ctxtab);
	nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
	nvkm_done(gr->ctxtab);
	return 0;
}

void *
nv20_gr_chan_dtor(struct nvkm_object *object)
{
	struct nv20_gr_chan *chan = nv20_gr_chan(object);
	nvkm_memory_unref(&chan->inst);
	return chan;
}

static const struct nvkm_object_func
nv20_gr_chan = {
	.dtor = nv20_gr_chan_dtor,
	.init = nv20_gr_chan_init,
	.fini = nv20_gr_chan_fini,
};

static int
nv20_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
		 const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
	struct nv20_gr *gr = nv20_gr(base);
	struct nv20_gr_chan *chan;
	int ret, i;

	if (!(chan = kzalloc_obj(*chan)))
		return -ENOMEM;
	nvkm_object_ctor(&nv20_gr_chan, oclass, &chan->object);
	chan->gr = gr;
	chan->chid = fifoch->id;
	*pobject = &chan->object;

	ret = nvkm_memory_new(gr->base.engine.subdev.device,
			      NVKM_MEM_TARGET_INST, 0x37f0, 16, true,

Annotation

Implementation Notes