drivers/gpu/drm/nouveau/nvkm/engine/mpeg/priv.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/nouveau/nvkm/engine/mpeg/priv.h

Extension

.h

Size

512 bytes

Lines

18

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• engine/mpeg.h

Detected Declarations

• struct nvkm_chan

Annotated Snippet

#ifndef __NVKM_MPEG_PRIV_H__
#define __NVKM_MPEG_PRIV_H__
#include <engine/mpeg.h>
struct nvkm_chan;

int nv31_mpeg_init(struct nvkm_engine *);
void nv31_mpeg_tile(struct nvkm_engine *, int, struct nvkm_fb_tile *);
extern const struct nvkm_object_func nv31_mpeg_object;

bool nv40_mpeg_mthd_dma(struct nvkm_device *, u32, u32);

int nv50_mpeg_init(struct nvkm_engine *);
void nv50_mpeg_intr(struct nvkm_engine *);

extern const struct nvkm_object_func nv50_mpeg_cclass;
#endif

Annotation

• Immediate include surface: `engine/mpeg.h`.
• Detected declarations: `struct nvkm_chan`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.