drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c- Extension
.c- Size
- 1542 bytes
- Lines
- 44
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
engine/vp.hnvif/class.h
Detected Declarations
function g84_vp_new
Annotated Snippet
#include <engine/vp.h>
#include <nvif/class.h>
static const struct nvkm_xtensa_func
g84_vp = {
.fifo_val = 0x111,
.unkd28 = 0x9c544,
.sclass = {
{ -1, -1, NV74_VP2 },
{}
}
};
int
g84_vp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_xtensa_new_(&g84_vp, device, type, inst, true, 0x00f000, pengine);
}
Annotation
- Immediate include surface: `engine/vp.h`, `nvif/class.h`.
- Detected declarations: `function g84_vp_new`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.