drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
Extension: .c
Size: 5661 bytes
Lines: 116
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

core/subdev.h
nvfw/flcn.h

Detected Declarations

function files
function loader_config_v1_dump
function flcn_bl_dmem_desc_dump
function flcn_bl_dmem_desc_v1_dump
function flcn_bl_dmem_desc_v2_dump

Annotated Snippet

#include <core/subdev.h>
#include <nvfw/flcn.h>

void
loader_config_dump(struct nvkm_subdev *subdev, const struct loader_config *hdr)
{
	nvkm_debug(subdev, "loaderConfig\n");
	nvkm_debug(subdev, "\tdmaIdx        : %d\n", hdr->dma_idx);
	nvkm_debug(subdev, "\tcodeDmaBase   : 0x%xx\n", hdr->code_dma_base);
	nvkm_debug(subdev, "\tcodeSizeTotal : 0x%x\n", hdr->code_size_total);
	nvkm_debug(subdev, "\tcodeSizeToLoad: 0x%x\n", hdr->code_size_to_load);
	nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
	nvkm_debug(subdev, "\tdataDmaBase   : 0x%x\n", hdr->data_dma_base);
	nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
	nvkm_debug(subdev, "\toverlayDmaBase: 0x%x\n", hdr->overlay_dma_base);
	nvkm_debug(subdev, "\targc          : 0x%08x\n", hdr->argc);
	nvkm_debug(subdev, "\targv          : 0x%08x\n", hdr->argv);
	nvkm_debug(subdev, "\tcodeDmaBase1  : 0x%x\n", hdr->code_dma_base1);
	nvkm_debug(subdev, "\tdataDmaBase1  : 0x%x\n", hdr->data_dma_base1);
	nvkm_debug(subdev, "\tovlyDmaBase1  : 0x%x\n", hdr->overlay_dma_base1);
}

void
loader_config_v1_dump(struct nvkm_subdev *subdev,
		      const struct loader_config_v1 *hdr)
{
	nvkm_debug(subdev, "loaderConfig\n");
	nvkm_debug(subdev, "\treserved      : 0x%08x\n", hdr->reserved);
	nvkm_debug(subdev, "\tdmaIdx        : %d\n", hdr->dma_idx);
	nvkm_debug(subdev, "\tcodeDmaBase   : 0x%llxx\n", hdr->code_dma_base);
	nvkm_debug(subdev, "\tcodeSizeTotal : 0x%x\n", hdr->code_size_total);
	nvkm_debug(subdev, "\tcodeSizeToLoad: 0x%x\n", hdr->code_size_to_load);
	nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
	nvkm_debug(subdev, "\tdataDmaBase   : 0x%llx\n", hdr->data_dma_base);
	nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
	nvkm_debug(subdev, "\toverlayDmaBase: 0x%llx\n", hdr->overlay_dma_base);
	nvkm_debug(subdev, "\targc          : 0x%08x\n", hdr->argc);
	nvkm_debug(subdev, "\targv          : 0x%08x\n", hdr->argv);
}

void
flcn_bl_dmem_desc_dump(struct nvkm_subdev *subdev,
		       const struct flcn_bl_dmem_desc *hdr)
{
	nvkm_debug(subdev, "flcnBlDmemDesc\n");
	nvkm_debug(subdev, "\treserved      : 0x%08x 0x%08x 0x%08x 0x%08x\n",
		   hdr->reserved[0], hdr->reserved[1], hdr->reserved[2],
		   hdr->reserved[3]);
	nvkm_debug(subdev, "\tsignature     : 0x%08x 0x%08x 0x%08x 0x%08x\n",
		   hdr->signature[0], hdr->signature[1], hdr->signature[2],
		   hdr->signature[3]);
	nvkm_debug(subdev, "\tctxDma        : %d\n", hdr->ctx_dma);
	nvkm_debug(subdev, "\tcodeDmaBase   : 0x%x\n", hdr->code_dma_base);
	nvkm_debug(subdev, "\tnonSecCodeOff : 0x%x\n", hdr->non_sec_code_off);
	nvkm_debug(subdev, "\tnonSecCodeSize: 0x%x\n", hdr->non_sec_code_size);
	nvkm_debug(subdev, "\tsecCodeOff    : 0x%x\n", hdr->sec_code_off);
	nvkm_debug(subdev, "\tsecCodeSize   : 0x%x\n", hdr->sec_code_size);
	nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
	nvkm_debug(subdev, "\tdataDmaBase   : 0x%x\n", hdr->data_dma_base);
	nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
	nvkm_debug(subdev, "\tcodeDmaBase1  : 0x%x\n", hdr->code_dma_base1);
	nvkm_debug(subdev, "\tdataDmaBase1  : 0x%x\n", hdr->data_dma_base1);
}

void
flcn_bl_dmem_desc_v1_dump(struct nvkm_subdev *subdev,
			  const struct flcn_bl_dmem_desc_v1 *hdr)
{
	nvkm_debug(subdev, "flcnBlDmemDesc\n");
	nvkm_debug(subdev, "\treserved      : 0x%08x 0x%08x 0x%08x 0x%08x\n",
		   hdr->reserved[0], hdr->reserved[1], hdr->reserved[2],
		   hdr->reserved[3]);
	nvkm_debug(subdev, "\tsignature     : 0x%08x 0x%08x 0x%08x 0x%08x\n",
		   hdr->signature[0], hdr->signature[1], hdr->signature[2],
		   hdr->signature[3]);
	nvkm_debug(subdev, "\tctxDma        : %d\n", hdr->ctx_dma);
	nvkm_debug(subdev, "\tcodeDmaBase   : 0x%llx\n", hdr->code_dma_base);
	nvkm_debug(subdev, "\tnonSecCodeOff : 0x%x\n", hdr->non_sec_code_off);
	nvkm_debug(subdev, "\tnonSecCodeSize: 0x%x\n", hdr->non_sec_code_size);
	nvkm_debug(subdev, "\tsecCodeOff    : 0x%x\n", hdr->sec_code_off);
	nvkm_debug(subdev, "\tsecCodeSize   : 0x%x\n", hdr->sec_code_size);
	nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
	nvkm_debug(subdev, "\tdataDmaBase   : 0x%llx\n", hdr->data_dma_base);
	nvkm_debug(subdev, "\tdataSize      : 0x%x\n", hdr->data_size);
}

void
flcn_bl_dmem_desc_v2_dump(struct nvkm_subdev *subdev,
			  const struct flcn_bl_dmem_desc_v2 *hdr)
{

Annotation

Immediate include surface: `core/subdev.h`, `nvfw/flcn.h`.
Detected declarations: `function files`, `function loader_config_v1_dump`, `function flcn_bl_dmem_desc_dump`, `function flcn_bl_dmem_desc_v1_dump`, `function flcn_bl_dmem_desc_v2_dump`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.