drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
Extension
.c
Size
5665 bytes
Lines
174
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (timing) {
			*ver = nvbios_rd08(bios, timing + 0);
			switch (*ver) {
			case 0x10:
				*hdr = nvbios_rd08(bios, timing + 1);
				*cnt = nvbios_rd08(bios, timing + 2);
				*len = nvbios_rd08(bios, timing + 3);
				*snr = 0;
				*ssz = 0;
				return timing;
			case 0x20:
				*hdr = nvbios_rd08(bios, timing + 1);
				*cnt = nvbios_rd08(bios, timing + 5);
				*len = nvbios_rd08(bios, timing + 2);
				*snr = nvbios_rd08(bios, timing + 4);
				*ssz = nvbios_rd08(bios, timing + 3);
				return timing;
			default:
				break;
			}
		}
	}

	return 0;
}

u32
nvbios_timingEe(struct nvkm_bios *bios, int idx,
		u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
	u8  snr, ssz;
	u32 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz);
	if (timing && idx < *cnt) {
		timing += *hdr + idx * (*len + (snr * ssz));
		*hdr = *len;
		*cnt = snr;
		*len = ssz;
		return timing;
	}
	return 0;
}

u32
nvbios_timingEp(struct nvkm_bios *bios, int idx,
		u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p)
{
	u32 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp;
	p->timing_ver = *ver;
	p->timing_hdr = *hdr;
	switch (!!data * *ver) {
	case 0x10:
		p->timing_10_WR    = nvbios_rd08(bios, data + 0x00);
		p->timing_10_WTR   = nvbios_rd08(bios, data + 0x01);
		p->timing_10_CL    = nvbios_rd08(bios, data + 0x02);
		p->timing_10_RC    = nvbios_rd08(bios, data + 0x03);
		p->timing_10_RFC   = nvbios_rd08(bios, data + 0x05);
		p->timing_10_RAS   = nvbios_rd08(bios, data + 0x07);
		p->timing_10_RP    = nvbios_rd08(bios, data + 0x09);
		p->timing_10_RCDRD = nvbios_rd08(bios, data + 0x0a);
		p->timing_10_RCDWR = nvbios_rd08(bios, data + 0x0b);
		p->timing_10_RRD   = nvbios_rd08(bios, data + 0x0c);
		p->timing_10_13    = nvbios_rd08(bios, data + 0x0d);
		p->timing_10_ODT   = nvbios_rd08(bios, data + 0x0e) & 0x07;
		if (p->ramcfg_ver >= 0x10)
			p->ramcfg_RON = nvbios_rd08(bios, data + 0x0e) & 0x07;

		p->timing_10_24  = 0xff;
		p->timing_10_21  = 0;
		p->timing_10_20  = 0;
		p->timing_10_CWL = 0;
		p->timing_10_18  = 0;
		p->timing_10_16  = 0;

		switch (min_t(u8, *hdr, 25)) {
		case 25:
			p->timing_10_24  = nvbios_rd08(bios, data + 0x18);
			fallthrough;
		case 24:
		case 23:
		case 22:
			p->timing_10_21  = nvbios_rd08(bios, data + 0x15);
			fallthrough;
		case 21:
			p->timing_10_20  = nvbios_rd08(bios, data + 0x14);
			fallthrough;
		case 20:
			p->timing_10_CWL = nvbios_rd08(bios, data + 0x13);
			fallthrough;
		case 19:
			p->timing_10_18  = nvbios_rd08(bios, data + 0x12);

Annotation

Implementation Notes