drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h- Extension
.h- Size
- 5610 bytes
- Lines
- 161
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct gk20a_clk_pllg_paramsstruct gk20a_pllstruct gk20a_clkfunction gk20a_pllg_is_enabledfunction gk20a_pllg_n_lo
Annotated Snippet
struct gk20a_clk_pllg_params {
u32 min_vco, max_vco;
u32 min_u, max_u;
u32 min_m, max_m;
u32 min_n, max_n;
u32 min_pl, max_pl;
};
struct gk20a_pll {
u32 m;
u32 n;
u32 pl;
};
struct gk20a_clk {
struct nvkm_clk base;
const struct gk20a_clk_pllg_params *params;
struct gk20a_pll pll;
u32 parent_rate;
struct gk20a_devfreq *devfreq;
u32 (*div_to_pl)(u32);
u32 (*pl_to_div)(u32);
};
#define gk20a_clk(p) container_of((p), struct gk20a_clk, base)
u32 gk20a_pllg_calc_rate(struct gk20a_clk *, struct gk20a_pll *);
int gk20a_pllg_calc_mnp(struct gk20a_clk *, unsigned long, struct gk20a_pll *);
void gk20a_pllg_read_mnp(struct gk20a_clk *, struct gk20a_pll *);
void gk20a_pllg_write_mnp(struct gk20a_clk *, const struct gk20a_pll *);
static inline bool
gk20a_pllg_is_enabled(struct gk20a_clk *clk)
{
struct nvkm_device *device = clk->base.subdev.device;
u32 val;
val = nvkm_rd32(device, GPCPLL_CFG);
return val & GPCPLL_CFG_ENABLE;
}
static inline u32
gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll)
{
return DIV_ROUND_UP(pll->m * clk->params->min_vco,
clk->parent_rate / KHZ);
}
int gk20a_clk_ctor(struct nvkm_device *, enum nvkm_subdev_type, int, const struct nvkm_clk_func *,
const struct gk20a_clk_pllg_params *, struct gk20a_clk *);
void gk20a_clk_fini(struct nvkm_clk *);
int gk20a_clk_read(struct nvkm_clk *, enum nv_clk_src);
int gk20a_clk_calc(struct nvkm_clk *, struct nvkm_cstate *);
int gk20a_clk_prog(struct nvkm_clk *);
void gk20a_clk_tidy(struct nvkm_clk *);
int gk20a_clk_setup_slide(struct gk20a_clk *);
#endif
Annotation
- Detected declarations: `struct gk20a_clk_pllg_params`, `struct gk20a_pll`, `struct gk20a_clk`, `function gk20a_pllg_is_enabled`, `function gk20a_pllg_n_lo`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.