drivers/gpu/drm/nouveau/nvkm/subdev/clk/gp10b.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gp10b.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gp10b.c
Extension
.c
Size
3442 bytes
Lines
186
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
#include <subdev/clk.h>
#include <subdev/timer.h>
#include <core/device.h>
#include <core/tegra.h>

#include "priv.h"
#include "gk20a_devfreq.h"
#include "gk20a.h"
#include "gp10b.h"

static int
gp10b_clk_init(struct nvkm_clk *base)
{
	struct gp10b_clk *clk = gp10b_clk(base);
	struct nvkm_subdev *subdev = &clk->base.subdev;
	int ret;

	/* Start with the highest frequency, matching the BPMP default */
	base->func->calc(base, &base->func->pstates[base->func->nr_pstates - 1].base);
	ret = base->func->prog(base);
	if (ret) {
		nvkm_error(subdev, "cannot initialize clock\n");
		return ret;
	}

	ret = gk20a_devfreq_init(base, &clk->devfreq);
	if (ret)
		return ret;

	return 0;
}

static int
gp10b_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
{
	struct gp10b_clk *clk = gp10b_clk(base);
	struct nvkm_subdev *subdev = &clk->base.subdev;

	switch (src) {
	case nv_clk_src_gpc:
		return clk_get_rate(clk->clk) / GK20A_CLK_GPC_MDIV;
	default:
		nvkm_error(subdev, "invalid clock source %d\n", src);
		return -EINVAL;
	}
}

static int
gp10b_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
{
	struct gp10b_clk *clk = gp10b_clk(base);
	u32 target_rate = cstate->domain[nv_clk_src_gpc] * GK20A_CLK_GPC_MDIV;

	clk->new_rate = clk_round_rate(clk->clk, target_rate) / GK20A_CLK_GPC_MDIV;

	return 0;
}

static int
gp10b_clk_prog(struct nvkm_clk *base)
{
	struct gp10b_clk *clk = gp10b_clk(base);
	int ret;

	ret = clk_set_rate(clk->clk, clk->new_rate * GK20A_CLK_GPC_MDIV);
	if (ret < 0)
		return ret;

	clk->rate = clk_get_rate(clk->clk) / GK20A_CLK_GPC_MDIV;

	return 0;
}

static struct nvkm_pstate
gp10b_pstates[] = {
	{
		.base = {
			.domain[nv_clk_src_gpc] = 114750,
		},
	},
	{
		.base = {
			.domain[nv_clk_src_gpc] = 216750,
		},
	},
	{
		.base = {
			.domain[nv_clk_src_gpc] = 318750,
		},

Annotation

Implementation Notes