drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c
Extension
.c
Size
5535 bytes
Lines
193
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include "nv50.h"

#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/pmu.h>
#include <subdev/pmu.h>
#include <subdev/timer.h>

static void
pmu_code(struct nv50_devinit *init, u32 pmu, u32 img, u32 len, bool sec)
{
	struct nvkm_device *device = init->base.subdev.device;
	struct nvkm_bios *bios = device->bios;
	int i;

	nvkm_wr32(device, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu);
	for (i = 0; i < len; i += 4) {
		if ((i & 0xff) == 0)
			nvkm_wr32(device, 0x10a188, (pmu + i) >> 8);
		nvkm_wr32(device, 0x10a184, nvbios_rd32(bios, img + i));
	}

	while (i & 0xff) {
		nvkm_wr32(device, 0x10a184, 0x00000000);
		i += 4;
	}
}

static void
pmu_data(struct nv50_devinit *init, u32 pmu, u32 img, u32 len)
{
	struct nvkm_device *device = init->base.subdev.device;
	struct nvkm_bios *bios = device->bios;
	int i;

	nvkm_wr32(device, 0x10a1c0, 0x01000000 | pmu);
	for (i = 0; i < len; i += 4)
		nvkm_wr32(device, 0x10a1c4, nvbios_rd32(bios, img + i));
}

static u32
pmu_args(struct nv50_devinit *init, u32 argp, u32 argi)
{
	struct nvkm_device *device = init->base.subdev.device;
	nvkm_wr32(device, 0x10a1c0, argp);
	nvkm_wr32(device, 0x10a1c0, nvkm_rd32(device, 0x10a1c4) + argi);
	return nvkm_rd32(device, 0x10a1c4);
}

static void
pmu_exec(struct nv50_devinit *init, u32 init_addr)
{
	struct nvkm_device *device = init->base.subdev.device;
	nvkm_wr32(device, 0x10a104, init_addr);
	nvkm_wr32(device, 0x10a10c, 0x00000000);
	nvkm_wr32(device, 0x10a100, 0x00000002);
}

static int
pmu_load(struct nv50_devinit *init, u8 type, bool post,
	 u32 *init_addr_pmu, u32 *args_addr_pmu)
{
	struct nvkm_subdev *subdev = &init->base.subdev;
	struct nvkm_bios *bios = subdev->device->bios;
	struct nvbios_pmuR pmu;
	int ret;

	if (!nvbios_pmuRm(bios, type, &pmu))
		return -EINVAL;

	if (!post || !subdev->device->pmu)
		return 0;

	ret = nvkm_falcon_reset(&subdev->device->pmu->falcon);
	if (ret)
		return ret;

	pmu_code(init, pmu.boot_addr_pmu, pmu.boot_addr, pmu.boot_size, false);
	pmu_code(init, pmu.code_addr_pmu, pmu.code_addr, pmu.code_size, true);
	pmu_data(init, pmu.data_addr_pmu, pmu.data_addr, pmu.data_size);

	if (init_addr_pmu) {
		*init_addr_pmu = pmu.init_addr_pmu;
		*args_addr_pmu = pmu.args_addr_pmu;
		return 0;
	}

	return pmu_exec(init, pmu.init_addr_pmu), 0;
}

Annotation

Implementation Notes