drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c- Extension
.c- Size
- 27531 bytes
- Lines
- 1008
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
ram.hramfuc.hcore/memory.hcore/option.hsubdev/bios.hsubdev/bios/M0205.hsubdev/bios/rammap.hsubdev/bios/timing.hsubdev/clk/gt215.hsubdev/gpio.h
Detected Declarations
struct gt215_ramfucstruct gt215_ltrainstruct gt215_ramfunction gt215_link_train_calcfunction gt215_link_train_initfunction gt215_link_train_finifunction gt215_ram_timing_calcfunction nvkm_sddr2_dll_resetfunction nvkm_sddr3_dll_disablefunction nvkm_gddr3_dll_disablefunction gt215_ram_lock_pllfunction gt215_ram_gpiofunction gt215_ram_calcfunction gt215_ram_progfunction gt215_ram_tidyfunction gt215_ram_initfunction gt215_ram_dtorfunction gt215_ram_new
Annotated Snippet
struct gt215_ramfuc {
struct ramfuc base;
struct ramfuc_reg r_0x001610;
struct ramfuc_reg r_0x001700;
struct ramfuc_reg r_0x002504;
struct ramfuc_reg r_0x004000;
struct ramfuc_reg r_0x004004;
struct ramfuc_reg r_0x004018;
struct ramfuc_reg r_0x004128;
struct ramfuc_reg r_0x004168;
struct ramfuc_reg r_0x100080;
struct ramfuc_reg r_0x100200;
struct ramfuc_reg r_0x100210;
struct ramfuc_reg r_0x100220[9];
struct ramfuc_reg r_0x100264;
struct ramfuc_reg r_0x1002d0;
struct ramfuc_reg r_0x1002d4;
struct ramfuc_reg r_0x1002dc;
struct ramfuc_reg r_0x10053c;
struct ramfuc_reg r_0x1005a0;
struct ramfuc_reg r_0x1005a4;
struct ramfuc_reg r_0x100700;
struct ramfuc_reg r_0x100714;
struct ramfuc_reg r_0x100718;
struct ramfuc_reg r_0x10071c;
struct ramfuc_reg r_0x100720;
struct ramfuc_reg r_0x100760;
struct ramfuc_reg r_0x1007a0;
struct ramfuc_reg r_0x1007e0;
struct ramfuc_reg r_0x100da0;
struct ramfuc_reg r_0x10f804;
struct ramfuc_reg r_0x1110e0;
struct ramfuc_reg r_0x111100;
struct ramfuc_reg r_0x111104;
struct ramfuc_reg r_0x1111e0;
struct ramfuc_reg r_0x111400;
struct ramfuc_reg r_0x611200;
struct ramfuc_reg r_mr[4];
struct ramfuc_reg r_gpio[4];
};
struct gt215_ltrain {
enum {
NVA3_TRAIN_UNKNOWN,
NVA3_TRAIN_UNSUPPORTED,
NVA3_TRAIN_ONCE,
NVA3_TRAIN_EXEC,
NVA3_TRAIN_DONE
} state;
u32 r_100720;
u32 r_1111e0;
u32 r_111400;
struct nvkm_memory *memory;
};
struct gt215_ram {
struct nvkm_ram base;
struct gt215_ramfuc fuc;
struct gt215_ltrain ltrain;
};
static void
gt215_link_train_calc(u32 *vals, struct gt215_ltrain *train)
{
int i, lo, hi;
u8 median[8], bins[4] = {0, 0, 0, 0}, bin = 0, qty = 0;
for (i = 0; i < 8; i++) {
for (lo = 0; lo < 0x40; lo++) {
if (!(vals[lo] & 0x80000000))
continue;
if (vals[lo] & (0x101 << i))
break;
}
if (lo == 0x40)
return;
for (hi = lo + 1; hi < 0x40; hi++) {
if (!(vals[lo] & 0x80000000))
continue;
if (!(vals[hi] & (0x101 << i))) {
hi--;
break;
}
}
median[i] = ((hi - lo) >> 1) + lo;
bins[(median[i] & 0xf0) >> 4]++;
median[i] += 0x30;
Annotation
- Immediate include surface: `ram.h`, `ramfuc.h`, `core/memory.h`, `core/option.h`, `subdev/bios.h`, `subdev/bios/M0205.h`, `subdev/bios/rammap.h`, `subdev/bios/timing.h`.
- Detected declarations: `struct gt215_ramfuc`, `struct gt215_ltrain`, `struct gt215_ram`, `function gt215_link_train_calc`, `function gt215_link_train_init`, `function gt215_link_train_fini`, `function gt215_ram_timing_calc`, `function nvkm_sddr2_dll_reset`, `function nvkm_sddr3_dll_disable`, `function nvkm_gddr3_dll_disable`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.