drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c

Extension

.c

Size

1637 bytes

Lines

43

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• ramnv40.h

Detected Declarations

• function files

Annotated Snippet

#include "ramnv40.h"

int
nv44_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
{
	struct nvkm_device *device = fb->subdev.device;
	u32  size = nvkm_rd32(device, 0x10020c) & 0xff000000;
	u32 fb474 = nvkm_rd32(device, 0x100474);
	enum nvkm_ram_type type = NVKM_RAM_TYPE_UNKNOWN;

	if (fb474 & 0x00000004)
		type = NVKM_RAM_TYPE_GDDR3;
	if (fb474 & 0x00000002)
		type = NVKM_RAM_TYPE_DDR2;
	if (fb474 & 0x00000001)
		type = NVKM_RAM_TYPE_DDR1;

	return nv40_ram_new_(fb, type, size, pram);
}

Annotation

• Immediate include surface: `ramnv40.h`.
• Detected declarations: `function files`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.