drivers/gpu/drm/nouveau/nvkm/subdev/fsp/gh100.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/subdev/fsp/gh100.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/nouveau/nvkm/subdev/fsp/gh100.c
Extension
.c
Size
6804 bytes
Lines
276
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

NVVAL_TEST(reply.mctp_header, MCTP, HEADER, EOM, !=, 1)) {
		nvkm_error(subdev, "unexpected MCTP header in reply: 0x%08x\n", reply.mctp_header);
		return -EIO;
	}

	if (NVDEF_TEST(reply.nvdm_header, MCTP, MSG_HEADER, TYPE, !=, VENDOR_PCI) ||
	    NVDEF_TEST(reply.nvdm_header, MCTP, MSG_HEADER, VENDOR_ID, !=, NV) ||
	    NVVAL_TEST(reply.nvdm_header, MCTP, MSG_HEADER, NVDM_TYPE, !=, NVDM_TYPE_FSP_RESPONSE)) {
		nvkm_error(subdev, "unexpected NVDM header in reply: 0x%08x\n", reply.nvdm_header);
		return -EIO;
	}

	if (reply.response.commandNvdmType != nvdm_type) {
		nvkm_error(subdev, "expected NVDM type 0x%02x in reply, got 0x%02x\n",
			   nvdm_type, reply.response.commandNvdmType);
		return -EIO;
	}

	if (reply.response.errorCode) {
		nvkm_error(subdev, "NVDM command 0x%02x failed with error 0x%08x\n",
			   nvdm_type, reply.response.errorCode);
		return -EIO;
	}

	return 0;
}

int
gh100_fsp_boot_gsp_fmc(struct nvkm_fsp *fsp, u64 args_addr, u32 rsvd_size, bool resume,
		       u64 img_addr, const u8 *hash, const u8 *pkey, const u8 *sig)
{
	struct {
		u32 mctp_header;
		u32 nvdm_header;
		NVDM_PAYLOAD_COT cot;
	} msg = {};

	msg.mctp_header = NVVAL(MCTP, HEADER, SOM, 1) |
			  NVVAL(MCTP, HEADER, EOM, 1) |
			  NVVAL(MCTP, HEADER, SEID, 0) |
			  NVVAL(MCTP, HEADER, SEQ, 0);

	msg.nvdm_header = NVDEF(MCTP, MSG_HEADER, TYPE, VENDOR_PCI) |
			  NVDEF(MCTP, MSG_HEADER, VENDOR_ID, NV) |
			  NVVAL(MCTP, MSG_HEADER, NVDM_TYPE, NVDM_TYPE_COT);

	msg.cot.version = fsp->func->cot.version;
	msg.cot.size = sizeof(msg.cot);
	msg.cot.gspFmcSysmemOffset = img_addr;
	if (!resume) {
		msg.cot.frtsVidmemOffset = ALIGN(rsvd_size, 0x200000);
		msg.cot.frtsVidmemSize = 0x100000;
	}

	memcpy(msg.cot.hash384, hash, fsp->func->cot.size_hash);
	memcpy(msg.cot.publicKey, pkey, fsp->func->cot.size_pkey);
	memcpy(msg.cot.signature, sig, fsp->func->cot.size_sig);

	msg.cot.gspBootArgsSysmemOffset = args_addr;

	return gh100_fsp_send_sync(fsp, NVDM_TYPE_COT, (const u8 *)&msg, sizeof(msg));
}

int
gh100_fsp_wait_secure_boot(struct nvkm_fsp *fsp)
{
	struct nvkm_device *device = fsp->subdev.device;
	unsigned timeout_ms = 4000;

	do {
		u32 status = NVKM_RD32(device, NV_THERM, I2CS_SCRATCH, FSP_BOOT_COMPLETE_STATUS);

		if (status == NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS)
			return 0;

		usleep_range(1000, 2000);
	} while (timeout_ms--);

	return -ETIMEDOUT;
}

static const struct nvkm_fsp_func
gh100_fsp = {
	.wait_secure_boot = gh100_fsp_wait_secure_boot,
	.cot = {
		.version = 1,
		.size_hash = 48,
		.size_pkey = 384,
		.size_sig = 384,
		.boot_gsp_fmc = gh100_fsp_boot_gsp_fmc,

Annotation

Implementation Notes