drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvrm/engine.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvrm/engine.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvrm/engine.h
Extension
.h
Size
15755 bytes
Lines
261
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __NVRM_ENGINE_H__
#define __NVRM_ENGINE_H__
#include <nvrm/nvtypes.h>

/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */

#define MC_ENGINE_IDX_NULL                          0 // This must be 0
#define MC_ENGINE_IDX_TMR                           1
#define MC_ENGINE_IDX_DISP                          2
#define MC_ENGINE_IDX_FB                            3
#define MC_ENGINE_IDX_FIFO                          4
#define MC_ENGINE_IDX_VIDEO                         5
#define MC_ENGINE_IDX_MD                            6
#define MC_ENGINE_IDX_BUS                           7
#define MC_ENGINE_IDX_PMGR                          8
#define MC_ENGINE_IDX_VP2                           9
#define MC_ENGINE_IDX_CIPHER                        10
#define MC_ENGINE_IDX_BIF                           11
#define MC_ENGINE_IDX_PPP                           12
#define MC_ENGINE_IDX_PRIVRING                      13
#define MC_ENGINE_IDX_PMU                           14
#define MC_ENGINE_IDX_CE0                           15
#define MC_ENGINE_IDX_CE1                           16
#define MC_ENGINE_IDX_CE2                           17
#define MC_ENGINE_IDX_CE3                           18
#define MC_ENGINE_IDX_CE4                           19
#define MC_ENGINE_IDX_CE5                           20
#define MC_ENGINE_IDX_CE6                           21
#define MC_ENGINE_IDX_CE7                           22
#define MC_ENGINE_IDX_CE8                           23
#define MC_ENGINE_IDX_CE9                           24
#define MC_ENGINE_IDX_CE_MAX                        MC_ENGINE_IDX_CE9
#define MC_ENGINE_IDX_VIC                           35
#define MC_ENGINE_IDX_ISOHUB                        36
#define MC_ENGINE_IDX_VGPU                          37
#define MC_ENGINE_IDX_MSENC                         38
#define MC_ENGINE_IDX_MSENC1                        39
#define MC_ENGINE_IDX_MSENC2                        40
#define MC_ENGINE_IDX_C2C                           41
#define MC_ENGINE_IDX_LTC                           42
#define MC_ENGINE_IDX_FBHUB                         43
#define MC_ENGINE_IDX_HDACODEC                      44
#define MC_ENGINE_IDX_GMMU                          45
#define MC_ENGINE_IDX_SEC2                          46
#define MC_ENGINE_IDX_FSP                           47
#define MC_ENGINE_IDX_NVLINK                        48
#define MC_ENGINE_IDX_GSP                           49
#define MC_ENGINE_IDX_NVJPG                         50
#define MC_ENGINE_IDX_NVJPEG                        MC_ENGINE_IDX_NVJPG
#define MC_ENGINE_IDX_NVJPEG0                       MC_ENGINE_IDX_NVJPEG
#define MC_ENGINE_IDX_NVJPEG1                       51
#define MC_ENGINE_IDX_NVJPEG2                       52
#define MC_ENGINE_IDX_NVJPEG3                       53
#define MC_ENGINE_IDX_NVJPEG4                       54
#define MC_ENGINE_IDX_NVJPEG5                       55
#define MC_ENGINE_IDX_NVJPEG6                       56
#define MC_ENGINE_IDX_NVJPEG7                       57
#define MC_ENGINE_IDX_REPLAYABLE_FAULT              58
#define MC_ENGINE_IDX_ACCESS_CNTR                   59
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT          60
#define MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR        61
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_ERROR    62
#define MC_ENGINE_IDX_INFO_FAULT                    63
#define MC_ENGINE_IDX_BSP                           64
#define MC_ENGINE_IDX_NVDEC                         MC_ENGINE_IDX_BSP
#define MC_ENGINE_IDX_NVDEC0                        MC_ENGINE_IDX_NVDEC
#define MC_ENGINE_IDX_NVDEC1                        65
#define MC_ENGINE_IDX_NVDEC2                        66
#define MC_ENGINE_IDX_NVDEC3                        67
#define MC_ENGINE_IDX_NVDEC4                        68
#define MC_ENGINE_IDX_NVDEC5                        69
#define MC_ENGINE_IDX_NVDEC6                        70
#define MC_ENGINE_IDX_NVDEC7                        71
#define MC_ENGINE_IDX_CPU_DOORBELL                  72
#define MC_ENGINE_IDX_PRIV_DOORBELL                 73
#define MC_ENGINE_IDX_MMU_ECC_ERROR                 74
#define MC_ENGINE_IDX_BLG                           75
#define MC_ENGINE_IDX_PERFMON                       76
#define MC_ENGINE_IDX_BUF_RESET                     77
#define MC_ENGINE_IDX_XBAR                          78
#define MC_ENGINE_IDX_ZPW                           79
#define MC_ENGINE_IDX_OFA0                          80
#define MC_ENGINE_IDX_TEGRA                         81
#define MC_ENGINE_IDX_GR                            82
#define MC_ENGINE_IDX_GR0                           MC_ENGINE_IDX_GR
#define MC_ENGINE_IDX_GR1                           83
#define MC_ENGINE_IDX_GR2                           84
#define MC_ENGINE_IDX_GR3                           85
#define MC_ENGINE_IDX_GR4                           86
#define MC_ENGINE_IDX_GR5                           87

Annotation

Implementation Notes