drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c

Extension

.c

Size

1868 bytes

Lines

51

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• priv.h
• core/pci.h

Detected Declarations

• function files
• function nv46_pci_new

Annotated Snippet

#include "priv.h"

#include <core/pci.h>

/* MSI re-arm through the PRI appears to be broken on NV46/NV50/G84/G86/G92,
 * so we access it via alternate PCI config space mechanisms.
 */
void
nv46_pci_msi_rearm(struct nvkm_pci *pci)
{
	struct nvkm_device *device = pci->subdev.device;
	struct pci_dev *pdev = device->func->pci(device)->pdev;
	pci_write_config_byte(pdev, 0x68, 0xff);
}

static const struct nvkm_pci_func
nv46_pci_func = {
	.cfg = { .addr = 0x088000, .size = 0x1000 },
	.msi_rearm = nv46_pci_msi_rearm,
};

int
nv46_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
	     struct nvkm_pci **ppci)
{
	return nvkm_pci_new_(&nv46_pci_func, device, type, inst, ppci);
}

Annotation

• Immediate include surface: `priv.h`, `core/pci.h`.
• Detected declarations: `function files`, `function nv46_pci_new`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.