drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/host.fuc

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/host.fuc

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/host.fuc
Extension
.fuc
Size
4549 bytes
Lines
151
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: drivers/gpu
Status
atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifdef INCLUDE_PROC
process(PROC_HOST, #host_init, #host_recv)
#endif

/******************************************************************************
 * HOST data segment
 *****************************************************************************/
#ifdef INCLUDE_DATA
// HOST (R)FIFO packet format
.equ #fifo_process 0x00
.equ #fifo_message 0x04
.equ #fifo_data0   0x08
.equ #fifo_data1   0x0c

// HOST HOST->PWR queue description
.equ #fifo_qlen 4 // log2(size of queue entry in bytes)
.equ #fifo_qnum 3 // log2(max number of entries in queue)
.equ #fifo_qmaskb (1 << #fifo_qnum) // max number of entries in queue
.equ #fifo_qmaskp (#fifo_qmaskb - 1)
.equ #fifo_qmaskf ((#fifo_qmaskb << 1) - 1)
.equ #fifo_qsize  (1 << (#fifo_qlen + #fifo_qnum))
fifo_queue: .skip 128 // #fifo_qsize

// HOST PWR->HOST queue description
.equ #rfifo_qlen 4 // log2(size of queue entry in bytes)
.equ #rfifo_qnum 3 // log2(max number of entries in queue)
.equ #rfifo_qmaskb (1 << #rfifo_qnum) // max number of entries in queue
.equ #rfifo_qmaskp (#rfifo_qmaskb - 1)
.equ #rfifo_qmaskf ((#rfifo_qmaskb << 1) - 1)
.equ #rfifo_qsize  (1 << (#rfifo_qlen + #rfifo_qnum))
rfifo_queue: .skip 128 // #rfifo_qsize
#endif

/******************************************************************************
 * HOST code segment
 *****************************************************************************/
#ifdef INCLUDE_CODE
// HOST->PWR comms - dequeue message(s) for process(es) from FIFO
//
// $r15 - current (host)
// $r0  - zero
host_send:
	nv_iord($r1, NV_PPWR_FIFO_GET(0))
	nv_iord($r2, NV_PPWR_FIFO_PUT(0))
	cmp b32 $r1 $r2
	bra e #host_send_done
		// calculate address of message
		and $r14 $r1 #fifo_qmaskp
		shl b32 $r14 $r14 #fifo_qlen
		add b32 $r14 #fifo_queue

		// read message data, and pass to appropriate process
		ld b32 $r11 D[$r14 + #fifo_data1]
		ld b32 $r12 D[$r14 + #fifo_data0]
		ld b32 $r13 D[$r14 + #fifo_message]
		ld b32 $r14 D[$r14 + #fifo_process]
		call(send)

		// increment GET
		add b32 $r1 0x1
		and $r14 $r1 #fifo_qmaskf
		nv_iowr(NV_PPWR_FIFO_GET(0), $r14)
		bra #host_send
	host_send_done:
	ret

// PWR->HOST comms - enqueue message for HOST to RFIFO
//
// $r15 - current (host)
// $r14 - process

Annotation

Implementation Notes