drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc- Extension
.fuc- Size
- 11972 bytes
- Lines
- 273
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: drivers/gpu
- Status
- atlas-only
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
os.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#define GT215 0xa3
#define GF100 0xc0
#define GF119 0xd9
#define GK208 0x108
#include "os.h"
// IO addresses
#define NV_PPWR_INTR_TRIGGER 0x0000
#define NV_PPWR_INTR_TRIGGER_USER1 0x00000080
#define NV_PPWR_INTR_TRIGGER_USER0 0x00000040
#define NV_PPWR_INTR_ACK 0x0004
#define NV_PPWR_INTR_ACK_SUBINTR 0x00000800
#define NV_PPWR_INTR_ACK_WATCHDOG 0x00000002
#define NV_PPWR_INTR 0x0008
#define NV_PPWR_INTR_SUBINTR 0x00000800
#define NV_PPWR_INTR_USER1 0x00000080
#define NV_PPWR_INTR_USER0 0x00000040
#define NV_PPWR_INTR_PAUSE 0x00000020
#define NV_PPWR_INTR_WATCHDOG 0x00000002
#define NV_PPWR_INTR_EN_SET 0x0010
#define NV_PPWR_INTR_EN_SET_SUBINTR 0x00000800
#define NV_PPWR_INTR_EN_SET_WATCHDOG 0x00000002
#define NV_PPWR_INTR_EN_CLR 0x0014
#define NV_PPWR_INTR_EN_CLR_MASK /* fuck i hate envyas */ -1
#define NV_PPWR_INTR_ROUTE 0x001c
#define NV_PPWR_TIMER_LOW 0x002c
#define NV_PPWR_WATCHDOG_TIME 0x0034
#define NV_PPWR_WATCHDOG_ENABLE 0x0038
#define NV_PPWR_CAPS 0x0108
#define NV_PPWR_UAS_CONFIG 0x0164
#define NV_PPWR_UAS_CONFIG_ENABLE 0x00010000
#if NVKM_PPWR_CHIPSET >= GK208
#define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x0450)
#endif
#define NV_PPWR_FIFO_PUT(i) (4 * (i) + 0x04a0)
#define NV_PPWR_FIFO_GET(i) (4 * (i) + 0x04b0)
#define NV_PPWR_FIFO_INTR 0x04c0
#define NV_PPWR_FIFO_INTR_EN 0x04c4
#define NV_PPWR_RFIFO_PUT 0x04c8
#define NV_PPWR_RFIFO_GET 0x04cc
#define NV_PPWR_H2D 0x04d0
#define NV_PPWR_D2H 0x04dc
#if NVKM_PPWR_CHIPSET < GK208
#define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x05d0)
#endif
#define NV_PPWR_SUBINTR 0x0688
#define NV_PPWR_SUBINTR_FIFO 0x00000002
#define NV_PPWR_MMIO_ADDR 0x07a0
#define NV_PPWR_MMIO_DATA 0x07a4
#define NV_PPWR_MMIO_CTRL 0x07ac
#define NV_PPWR_MMIO_CTRL_TRIGGER 0x00010000
#define NV_PPWR_MMIO_CTRL_STATUS 0x00007000
#define NV_PPWR_MMIO_CTRL_STATUS_IDLE 0x00000000
#define NV_PPWR_MMIO_CTRL_MASK 0x000000f0
#define NV_PPWR_MMIO_CTRL_MASK_B32_0 0x000000f0
#define NV_PPWR_MMIO_CTRL_OP 0x00000003
#define NV_PPWR_MMIO_CTRL_OP_RD 0x00000001
#define NV_PPWR_MMIO_CTRL_OP_WR 0x00000002
#define NV_PPWR_OUTPUT 0x07c0
#define NV_PPWR_OUTPUT_FB_PAUSE 0x00000004
#if NVKM_PPWR_CHIPSET < GF119
#define NV_PPWR_OUTPUT_I2C_3_SCL 0x00000100
#define NV_PPWR_OUTPUT_I2C_3_SDA 0x00000200
#define NV_PPWR_OUTPUT_I2C_0_SCL 0x00001000
#define NV_PPWR_OUTPUT_I2C_0_SDA 0x00002000
#define NV_PPWR_OUTPUT_I2C_1_SCL 0x00004000
#define NV_PPWR_OUTPUT_I2C_1_SDA 0x00008000
#define NV_PPWR_OUTPUT_I2C_2_SCL 0x00010000
#define NV_PPWR_OUTPUT_I2C_2_SDA 0x00020000Annotation
- Immediate include surface: `os.h`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.