drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc

Extension

.fuc

Size

9182 bytes

Lines

448

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: drivers/gpu

Status

atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifdef INCLUDE_PROC
process(PROC_MEMX, #memx_init, #memx_recv)
#endif

/******************************************************************************
 * MEMX data segment
 *****************************************************************************/
#ifdef INCLUDE_DATA
.equ #memx_opcode 0
.equ #memx_header 2
.equ #memx_length 4
.equ #memx_func   8

#define handler(cmd,hdr,len,func) /*
*/	.b16 MEMX_##cmd /*
*/	.b16 hdr /*
*/	.b16 len /*
*/      .b16 0 /*
*/	.b32 func

memx_func_head:
handler(ENTER , 0x0000, 0x0000, #memx_func_enter)
memx_func_next:
handler(LEAVE , 0x0000, 0x0000, #memx_func_leave)
handler(WR32  , 0x0000, 0x0002, #memx_func_wr32)
handler(WAIT  , 0x0004, 0x0000, #memx_func_wait)
handler(DELAY , 0x0001, 0x0000, #memx_func_delay)
handler(VBLANK, 0x0001, 0x0000, #memx_func_wait_vblank)
handler(TRAIN , 0x0000, 0x0000, #memx_func_train)
memx_func_tail:

.equ #memx_func_size #memx_func_next - #memx_func_head
.equ #memx_func_num (#memx_func_tail - #memx_func_head) / #memx_func_size

memx_ts_start:
.b32 0
memx_ts_end:
.b32 0

memx_data_head:
.skip 0x0800
memx_data_tail:

memx_train_head:
.skip 0x0100
memx_train_tail:
#endif

/******************************************************************************
 * MEMX code segment
 *****************************************************************************/
#ifdef INCLUDE_CODE
// description
//
// $r15 - current (memx)
// $r4  - packet length
// $r3  - opcode desciption
// $r0  - zero
memx_func_enter:
#if NVKM_PPWR_CHIPSET == GT215
	mov $r8 0x1610
	nv_rd32($r7, $r8)
	imm32($r6, 0xfffffffc)
	and $r7 $r6
	mov $r6 0x2
	or $r7 $r6
	nv_wr32($r8, $r7)
#else
	mov $r6 0x001620
	imm32($r7, ~0x00000aa2);

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.