drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c- Extension
.c- Size
- 2890 bytes
- Lines
- 86
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
priv.h
Detected Declarations
function filesfunction gm200_pmu_flcn_bind_instfunction gm200_pmu_nofwfunction gm200_pmu_new
Annotated Snippet
#include "priv.h"
static int
gm200_pmu_flcn_bind_stat(struct nvkm_falcon *falcon, bool intr)
{
nvkm_falcon_wr32(falcon, 0x200, 0x0000030e);
return (nvkm_falcon_rd32(falcon, 0x20c) & 0x00007000) >> 12;
}
void
gm200_pmu_flcn_bind_inst(struct nvkm_falcon *falcon, int target, u64 addr)
{
nvkm_falcon_wr32(falcon, 0xe00, 4); /* DMAIDX_UCODE */
nvkm_falcon_wr32(falcon, 0xe04, 0); /* DMAIDX_VIRT */
nvkm_falcon_wr32(falcon, 0xe08, 4); /* DMAIDX_PHYS_VID */
nvkm_falcon_wr32(falcon, 0xe0c, 5); /* DMAIDX_PHYS_SYS_COH */
nvkm_falcon_wr32(falcon, 0xe10, 6); /* DMAIDX_PHYS_SYS_NCOH */
nvkm_falcon_mask(falcon, 0x090, 0x00010000, 0x00010000);
nvkm_falcon_wr32(falcon, 0x480, (1 << 30) | (target << 28) | (addr >> 12));
}
const struct nvkm_falcon_func
gm200_pmu_flcn = {
.disable = gm200_flcn_disable,
.enable = gm200_flcn_enable,
.reset_pmc = true,
.reset_wait_mem_scrubbing = gm200_flcn_reset_wait_mem_scrubbing,
.debug = 0xc08,
.bind_inst = gm200_pmu_flcn_bind_inst,
.bind_stat = gm200_pmu_flcn_bind_stat,
.imem_pio = &gm200_flcn_imem_pio,
.dmem_pio = &gm200_flcn_dmem_pio,
.start = nvkm_falcon_v1_start,
.cmdq = { 0x4a0, 0x4b0, 4 },
.msgq = { 0x4c8, 0x4cc, 0 },
};
static const struct nvkm_pmu_func
gm200_pmu = {
.flcn = &gm200_pmu_flcn,
.reset = gf100_pmu_reset,
};
int
gm200_pmu_nofw(struct nvkm_pmu *pmu, int ver, const struct nvkm_pmu_fwif *fwif)
{
nvkm_warn(&pmu->subdev, "firmware unavailable\n");
return 0;
}
static const struct nvkm_pmu_fwif
gm200_pmu_fwif[] = {
{ -1, gm200_pmu_nofw, &gm200_pmu },
{}
};
int
gm200_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_pmu **ppmu)
{
return nvkm_pmu_new_(gm200_pmu_fwif, device, type, inst, ppmu);
}
Annotation
- Immediate include surface: `priv.h`.
- Detected declarations: `function files`, `function gm200_pmu_flcn_bind_inst`, `function gm200_pmu_nofw`, `function gm200_pmu_new`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.