drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c
Extension
.c
Size
4243 bytes
Lines
134
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <core/device.h>

#include "priv.h"
#include "gk104.h"

void
gk104_clkgate_enable(struct nvkm_therm *base)
{
	struct gk104_therm *therm = gk104_therm(base);
	struct nvkm_device *dev = therm->base.subdev.device;
	const struct gk104_clkgate_engine_info *order = therm->clkgate_order;
	int i;

	/* Program ENG_MANT, ENG_FILTER */
	for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) {
		if (!nvkm_device_subdev(dev, order[i].type, order[i].inst))
			continue;

		nvkm_mask(dev, 0x20200 + order[i].offset, 0xff00, 0x4500);
	}

	/* magic */
	nvkm_wr32(dev, 0x020288, therm->idle_filter->fecs);
	nvkm_wr32(dev, 0x02028c, therm->idle_filter->hubmmu);

	/* Enable clockgating (ENG_CLK = RUN->AUTO) */
	for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) {
		if (!nvkm_device_subdev(dev, order[i].type, order[i].inst))
			continue;

		nvkm_mask(dev, 0x20200 + order[i].offset, 0x00ff, 0x0045);
	}
}

void
gk104_clkgate_fini(struct nvkm_therm *base, bool suspend)
{
	struct gk104_therm *therm = gk104_therm(base);
	struct nvkm_device *dev = therm->base.subdev.device;
	const struct gk104_clkgate_engine_info *order = therm->clkgate_order;
	int i;

	/* ENG_CLK = AUTO->RUN, ENG_PWR = RUN->AUTO */
	for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) {
		if (!nvkm_device_subdev(dev, order[i].type, order[i].inst))
			continue;

		nvkm_mask(dev, 0x20200 + order[i].offset, 0xff, 0x54);
	}
}

const struct gk104_clkgate_engine_info gk104_clkgate_engine_info[] = {
	{ NVKM_ENGINE_GR,     0, 0x00 },
	{ NVKM_ENGINE_MSPDEC, 0, 0x04 },
	{ NVKM_ENGINE_MSPPP,  0, 0x08 },
	{ NVKM_ENGINE_MSVLD,  0, 0x0c },
	{ NVKM_ENGINE_CE,     0, 0x10 },
	{ NVKM_ENGINE_CE,     1, 0x14 },
	{ NVKM_ENGINE_MSENC,  0, 0x18 },
	{ NVKM_ENGINE_CE,     2, 0x1c },
	{ NVKM_SUBDEV_NR },
};

const struct gf100_idle_filter gk104_idle_filter = {
	.fecs = 0x00001000,
	.hubmmu = 0x00001000,
};

static const struct nvkm_therm_func
gk104_therm_func = {
	.init = gf119_therm_init,
	.fini = g84_therm_fini,
	.pwm_ctrl = gf119_fan_pwm_ctrl,
	.pwm_get = gf119_fan_pwm_get,
	.pwm_set = gf119_fan_pwm_set,
	.pwm_clock = gf119_fan_pwm_clock,
	.temp_get = g84_temp_get,
	.fan_sense = gt215_therm_fan_sense,
	.program_alarms = nvkm_therm_program_alarms_polling,
	.clkgate_init = gf100_clkgate_init,
	.clkgate_enable = gk104_clkgate_enable,
	.clkgate_fini = gk104_clkgate_fini,
};

static int
gk104_therm_new_(const struct nvkm_therm_func *func, struct nvkm_device *device,
		 enum nvkm_subdev_type type, int inst,
		 const struct gk104_clkgate_engine_info *clkgate_order,
		 const struct gf100_idle_filter *idle_filter,
		 struct nvkm_therm **ptherm)

Annotation

Implementation Notes