drivers/gpu/drm/omapdrm/dss/dispc.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/omapdrm/dss/dispc.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/omapdrm/dss/dispc.c
Extension
.c
Size
127501 bytes
Lines
4777
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dispc_features {
	u8 sw_start;
	u8 fp_start;
	u8 bp_start;
	u16 sw_max;
	u16 vp_max;
	u16 hp_max;
	u8 mgr_width_start;
	u8 mgr_height_start;
	u16 mgr_width_max;
	u16 mgr_height_max;
	u16 ovl_width_max;
	u16 ovl_height_max;
	unsigned long max_lcd_pclk;
	unsigned long max_tv_pclk;
	unsigned int max_downscale;
	unsigned int max_line_width;
	unsigned int min_pcd;
	int (*calc_scaling)(struct dispc_device *dispc,
		unsigned long pclk, unsigned long lclk,
		const struct videomode *vm,
		u16 width, u16 height, u16 out_width, u16 out_height,
		u32 fourcc, bool *five_taps,
		int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
		u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
	unsigned long (*calc_core_clk) (unsigned long pclk,
		u16 width, u16 height, u16 out_width, u16 out_height,
		bool mem_to_mem);
	u8 num_fifos;
	const enum dispc_feature_id *features;
	unsigned int num_features;
	const struct dss_reg_field *reg_fields;
	const unsigned int num_reg_fields;
	const enum omap_overlay_caps *overlay_caps;
	const u32 **supported_color_modes;
	const u32 *supported_scaler_color_modes;
	unsigned int num_mgrs;
	unsigned int num_ovls;
	unsigned int buffer_size_unit;
	unsigned int burst_size_unit;

	/* swap GFX & WB fifos */
	bool gfx_fifo_workaround:1;

	/* no DISPC_IRQ_FRAMEDONETV on this SoC */
	bool no_framedone_tv:1;

	/* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
	bool mstandby_workaround:1;

	bool set_max_preload:1;

	/* PIXEL_INC is not added to the last pixel of a line */
	bool last_pixel_inc_missing:1;

	/* POL_FREQ has ALIGN bit */
	bool supports_sync_align:1;

	bool has_writeback:1;

	bool supports_double_pixel:1;

	/*
	 * Field order for VENC is different than HDMI. We should handle this in
	 * some intelligent manner, but as the SoCs have either HDMI or VENC,
	 * never both, we can just use this flag for now.
	 */
	bool reverse_ilace_field_order:1;

	bool has_gamma_table:1;

	bool has_gamma_i734_bug:1;
};

#define DISPC_MAX_NR_FIFOS 5
#define DISPC_MAX_CHANNEL_GAMMA 4

struct dispc_device {
	struct platform_device *pdev;
	void __iomem    *base;
	struct dss_device *dss;

	struct dss_debugfs_entry *debugfs;

	int irq;
	irq_handler_t user_handler;
	void *user_data;

	unsigned long core_clk_rate;
	unsigned long tv_pclk_rate;

Annotation

Implementation Notes