drivers/gpu/drm/panel/panel-boe-bf060y8m-aj0.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/panel/panel-boe-bf060y8m-aj0.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/panel/panel-boe-bf060y8m-aj0.c
Extension
.c
Size
11502 bytes
Lines
402
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct boe_bf060y8m_aj0 {
	struct drm_panel panel;
	struct mipi_dsi_device *dsi;
	struct regulator_bulk_data vregs[BF060Y8M_VREG_MAX];
	struct gpio_desc *reset_gpio;
};

static inline
struct boe_bf060y8m_aj0 *to_boe_bf060y8m_aj0(struct drm_panel *panel)
{
	return container_of(panel, struct boe_bf060y8m_aj0, panel);
}

static void boe_bf060y8m_aj0_reset(struct boe_bf060y8m_aj0 *boe)
{
	gpiod_set_value_cansleep(boe->reset_gpio, 0);
	usleep_range(2000, 3000);
	gpiod_set_value_cansleep(boe->reset_gpio, 1);
	usleep_range(15000, 16000);
	gpiod_set_value_cansleep(boe->reset_gpio, 0);
	usleep_range(5000, 6000);
}

static int boe_bf060y8m_aj0_on(struct boe_bf060y8m_aj0 *boe)
{
	struct mipi_dsi_device *dsi = boe->dsi;
	struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };

	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0xa5, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x00, 0x4c);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_3D_CONTROL, 0x10);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, DCS_ALLOW_HBM_RANGE);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf8,
				     0x00, 0x08, 0x10, 0x00, 0x22, 0x00, 0x00, 0x2d);

	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
	mipi_dsi_msleep(&dsi_ctx, 30);

	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0xa5, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc0,
				     0x08, 0x48, 0x65, 0x33, 0x33, 0x33,
				     0x2a, 0x31, 0x39, 0x20, 0x09);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc1, 0x00, 0x00, 0x00, 0x1f, 0x1f,
				     0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f,
				     0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2, 0x20, 0x04, 0x10, 0x12, 0x92,
				     0x4f, 0x8f, 0x44, 0x84, 0x83, 0x83, 0x83,
				     0x5c, 0x5c, 0x5c);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xde, 0x01, 0x2c, 0x00, 0x77, 0x3e);

	mipi_dsi_msleep(&dsi_ctx, 30);

	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
	mipi_dsi_msleep(&dsi_ctx, 50);

	return dsi_ctx.accum_err;
}

static void boe_bf060y8m_aj0_off(struct boe_bf060y8m_aj0 *boe)
{
	struct mipi_dsi_device *dsi = boe->dsi;
	struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };

	/* OFF commands sent in HS mode */
	dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
	mipi_dsi_msleep(&dsi_ctx, 20);

	mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
	mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000);
	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
}

static int boe_bf060y8m_aj0_prepare(struct drm_panel *panel)
{
	struct boe_bf060y8m_aj0 *boe = to_boe_bf060y8m_aj0(panel);
	int ret;

	/*
	 * Enable EL Driving Voltage first - doing that at the beginning
	 * or at the end of the power sequence doesn't matter, so enable
	 * it here to avoid yet another usleep at the end.
	 */
	ret = regulator_enable(boe->vregs[BF060Y8M_VREG_EL_VDD].consumer);
	if (ret)
		return ret;
	ret = regulator_enable(boe->vregs[BF060Y8M_VREG_EL_VSS].consumer);
	if (ret)
		goto err_elvss;

Annotation

Implementation Notes