drivers/gpu/drm/panel/panel-feixin-k101-im2ba02.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/panel/panel-feixin-k101-im2ba02.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/panel/panel-feixin-k101-im2ba02.c
Extension
.c
Size
13223 bytes
Lines
514
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct k101_im2ba02 {
	struct drm_panel	panel;
	struct mipi_dsi_device	*dsi;

	struct regulator_bulk_data supplies[ARRAY_SIZE(regulator_names)];
	struct gpio_desc	*reset;
};

static inline struct k101_im2ba02 *panel_to_k101_im2ba02(struct drm_panel *panel)
{
	return container_of(panel, struct k101_im2ba02, panel);
}

struct k101_im2ba02_init_cmd {
	u8 data[K101_IM2BA02_INIT_CMD_LEN];
};

static const struct k101_im2ba02_init_cmd k101_im2ba02_init_cmds[] = {
	/* Switch to page 0 */
	{ .data = { 0xE0, 0x00 } },

	/* Seems to be some password */
	{ .data = { 0xE1, 0x93} },
	{ .data = { 0xE2, 0x65 } },
	{ .data = { 0xE3, 0xF8 } },

	/* Lane number, 0x02 - 3 lanes, 0x03 - 4 lanes */
	{ .data = { 0x80, 0x03 } },

	/* Sequence control */
	{ .data = { 0x70, 0x02 } },
	{ .data = { 0x71, 0x23 } },
	{ .data = { 0x72, 0x06 } },

	/* Switch to page 1 */
	{ .data = { 0xE0, 0x01 } },

	/* Set VCOM */
	{ .data = { 0x00, 0x00 } },
	{ .data = { 0x01, 0x66 } },
	/* Set VCOM_Reverse */
	{ .data = { 0x03, 0x00 } },
	{ .data = { 0x04, 0x25 } },

	/* Set Gamma Power, VG[MS][PN] */
	{ .data = { 0x17, 0x00 } },
	{ .data = { 0x18, 0x6D } },
	{ .data = { 0x19, 0x00 } },
	{ .data = { 0x1A, 0x00 } },
	{ .data = { 0x1B, 0xBF } }, /* VGMN = -4.5V */
	{ .data = { 0x1C, 0x00 } },

	/* Set Gate Power */
	{ .data = { 0x1F, 0x3E } }, /* VGH_R = 15V */
	{ .data = { 0x20, 0x28 } }, /* VGL_R = -11V */
	{ .data = { 0x21, 0x28 } }, /* VGL_R2 = -11V */
	{ .data = { 0x22, 0x0E } }, /* PA[6:4] = 0, PA[0] = 0 */

	/* Set Panel */
	{ .data = { 0x37, 0x09 } }, /* SS = 1, BGR = 1 */

	/* Set RGBCYC */
	{ .data = { 0x38, 0x04 } }, /* JDT = 100 column inversion */
	{ .data = { 0x39, 0x08 } }, /* RGB_N_EQ1 */
	{ .data = { 0x3A, 0x12 } }, /* RGB_N_EQ2 */
	{ .data = { 0x3C, 0x78 } }, /* set EQ3 for TE_H */
	{ .data = { 0x3D, 0xFF } }, /* set CHGEN_ON */
	{ .data = { 0x3E, 0xFF } }, /* set CHGEN_OFF */
	{ .data = { 0x3F, 0x7F } }, /* set CHGEN_OFF2 */

	/* Set TCON parameter */
	{ .data = { 0x40, 0x06 } }, /* RSO = 800 points */
	{ .data = { 0x41, 0xA0 } }, /* LN = 1280 lines */

	/* Set power voltage */
	{ .data = { 0x55, 0x0F } }, /* DCDCM */
	{ .data = { 0x56, 0x01 } },
	{ .data = { 0x57, 0x69 } },
	{ .data = { 0x58, 0x0A } },
	{ .data = { 0x59, 0x0A } },
	{ .data = { 0x5A, 0x45 } },
	{ .data = { 0x5B, 0x15 } },

	/* Set gamma */
	{ .data = { 0x5D, 0x7C } },
	{ .data = { 0x5E, 0x65 } },
	{ .data = { 0x5F, 0x55 } },
	{ .data = { 0x60, 0x49 } },
	{ .data = { 0x61, 0x44 } },
	{ .data = { 0x62, 0x35 } },

Annotation

Implementation Notes