drivers/gpu/drm/panel/panel-himax-hx83112a.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/panel/panel-himax-hx83112a.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/panel/panel-himax-hx83112a.c
Extension
.c
Size
12535 bytes
Lines
348
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hx83112a_panel {
	struct drm_panel panel;
	struct mipi_dsi_device *dsi;
	struct regulator_bulk_data supplies[3];
	struct gpio_desc *reset_gpio;
};

static inline struct hx83112a_panel *to_hx83112a_panel(struct drm_panel *panel)
{
	return container_of(panel, struct hx83112a_panel, panel);
}

static void hx83112a_reset(struct hx83112a_panel *ctx)
{
	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
	msleep(20);
	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
	msleep(20);
	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
	msleep(50);
}

static int hx83112a_on(struct mipi_dsi_device *dsi)
{
	struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };

	dsi->mode_flags |= MIPI_DSI_MODE_LPM;

	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETEXTC, 0x83, 0x11, 0x2a);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETPOWER1,
				     0x08, 0x28, 0x28, 0x83, 0x83, 0x4c, 0x4f, 0x33);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDISP,
				     0x00, 0x02, 0x00, 0x90, 0x24, 0x00, 0x08, 0x19,
				     0xea, 0x11, 0x11, 0x00, 0x11, 0xa3);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDRV,
				     0x58, 0x68, 0x58, 0x68, 0x0f, 0xef, 0x0b, 0xc0,
				     0x0b, 0xc0, 0x0b, 0xc0, 0x00, 0xff, 0x00, 0xff,
				     0x00, 0x00, 0x14, 0x15, 0x00, 0x29, 0x11, 0x07,
				     0x12, 0x00, 0x29);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x02);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDRV,
				     0x00, 0x12, 0x12, 0x11, 0x88, 0x12, 0x12, 0x00,
				     0x53);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x03);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDGCLUT,
				     0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6,
				     0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6,
				     0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d,
				     0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49,
				     0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a,
				     0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3,
				     0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad,
				     0x40);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x02);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDGCLUT,
				     0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6,
				     0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6,
				     0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d,
				     0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49,
				     0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a,
				     0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3,
				     0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad,
				     0x40);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x01);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDGCLUT,
				     0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6,
				     0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6,
				     0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d,
				     0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49,
				     0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a,
				     0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3,
				     0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad,
				     0x40);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDGCLUT, 0x01);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETTCON,
				     0x70, 0x00, 0x04, 0xe0, 0x33, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETPANEL, 0x08);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETPOWER2, 0x2b, 0x2b);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETGIP0,
				     0x80, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x08,
				     0x08, 0x03, 0x03, 0x22, 0x18, 0x07, 0x07, 0x07,
				     0x07, 0x32, 0x10, 0x06, 0x00, 0x06, 0x32, 0x10,
				     0x07, 0x00, 0x07, 0x32, 0x19, 0x31, 0x09, 0x31,
				     0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x08,
				     0x09, 0x30, 0x00, 0x00, 0x00, 0x06, 0x0d, 0x00,
				     0x0f);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x01);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETGIP0,

Annotation

Implementation Notes