drivers/gpu/drm/panel/panel-himax-hx83112b.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/panel/panel-himax-hx83112b.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/panel/panel-himax-hx83112b.c
Extension
.c
Size
15623 bytes
Lines
431
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hx83112b_panel {
	struct drm_panel panel;
	struct mipi_dsi_device *dsi;
	struct regulator_bulk_data *supplies;
	struct gpio_desc *reset_gpio;
};

static const struct regulator_bulk_data hx83112b_supplies[] = {
	{ .supply = "iovcc" },
	{ .supply = "vsn" },
	{ .supply = "vsp" },
};

static inline struct hx83112b_panel *to_hx83112b_panel(struct drm_panel *panel)
{
	return container_of(panel, struct hx83112b_panel, panel);
}

static void hx83112b_reset(struct hx83112b_panel *ctx)
{
	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
	usleep_range(10000, 11000);
	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
	usleep_range(10000, 11000);
	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
	usleep_range(10000, 11000);
}

static int hx83112b_on(struct hx83112b_panel *ctx)
{
	struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };

	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETEXTC, 0x83, 0x11, 0x2b);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x01);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDISMO, 0x08, 0x70);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x03);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDISP, 0x04, 0x38, 0x08, 0x70);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETPOWER1,
				     0xf8, 0x27, 0x27, 0x00, 0x00, 0x0b, 0x0e,
				     0x0b, 0x0e, 0x33);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETPOWER2, 0x2d, 0x2d);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDISP,
				     0x80, 0x02, 0x18, 0x80, 0x70, 0x00, 0x08,
				     0x1c, 0x08, 0x11, 0x05);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_UNKNOWN4, 0xd1);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDISP, 0x00, 0x08);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_UNKNOWN4, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x02);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDISP, 0xb5, 0x0a);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETIDLE,
				     0x00, 0x00, 0x08, 0x1c, 0x08, 0x34, 0x34,
				     0x88);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDRV,
				     0x65, 0x6b, 0x00, 0x00, 0xd0, 0xd4, 0x36,
				     0xcf, 0x06, 0xce, 0x00, 0xce, 0x00, 0x00,
				     0x00, 0x07, 0x00, 0x2a, 0x07, 0x01, 0x07,
				     0x00, 0x00, 0x2a);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x03);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_UNKNOWN4, 0xc3);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDRV, 0x01, 0x67, 0x2a);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_UNKNOWN4, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDGCLUT, 0x01);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x01);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDGCLUT,
				     0xff, 0xfb, 0xf9, 0xf6, 0xf4, 0xf1, 0xef,
				     0xea, 0xe7, 0xe5, 0xe2, 0xdf, 0xdd, 0xda,
				     0xd8, 0xd5, 0xd2, 0xcf, 0xcc, 0xc5, 0xbe,
				     0xb7, 0xb0, 0xa8, 0xa0, 0x98, 0x8e, 0x85,
				     0x7b, 0x72, 0x69, 0x5e, 0x53, 0x48, 0x3e,
				     0x35, 0x2b, 0x22, 0x17, 0x0d, 0x09, 0x07,
				     0x05, 0x01, 0x00, 0x26, 0xf0, 0x86, 0x25,
				     0x6e, 0xb6, 0xdd, 0xf3, 0xd8, 0xcc, 0x9b,
				     0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x02);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDGCLUT,
				     0xff, 0xfb, 0xf9, 0xf6, 0xf4, 0xf1, 0xef,
				     0xea, 0xe7, 0xe5, 0xe2, 0xdf, 0xdd, 0xda,
				     0xd8, 0xd5, 0xd2, 0xcf, 0xcc, 0xc5, 0xbe,
				     0xb7, 0xb0, 0xa8, 0xa0, 0x98, 0x8e, 0x85,
				     0x7b, 0x72, 0x69, 0x5e, 0x53, 0x48, 0x3e,
				     0x35, 0x2b, 0x22, 0x17, 0x0d, 0x09, 0x07,
				     0x05, 0x01, 0x00, 0x26, 0xf0, 0x86, 0x25,
				     0x6e, 0xb6, 0xdd, 0xf3, 0xd8, 0xcc, 0x9b,
				     0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x03);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDGCLUT,
				     0xff, 0xfb, 0xf9, 0xf6, 0xf4, 0xf1, 0xef,

Annotation

Implementation Notes