drivers/gpu/drm/panel/panel-ilitek-ili9322.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/panel/panel-ilitek-ili9322.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/panel/panel-ilitek-ili9322.c
Extension
.c
Size
25975 bytes
Lines
942
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ili9322_config {
	u32 width_mm;
	u32 height_mm;
	bool flip_horizontal;
	bool flip_vertical;
	enum ili9322_input input;
	u32 vreg1out_mv;
	u32 vcom_high_percent;
	u32 vcom_amplitude_percent;
	bool dclk_active_high;
	bool de_active_high;
	bool hsync_active_high;
	bool vsync_active_high;
	u8 syncmode;
	u8 gamma_corr_pos[8];
	u8 gamma_corr_neg[8];
};

struct ili9322 {
	struct device *dev;
	const struct ili9322_config *conf;
	struct drm_panel panel;
	struct regmap *regmap;
	struct regulator_bulk_data supplies[3];
	struct gpio_desc *reset_gpio;
	enum ili9322_input input;
	struct videomode vm;
	u8 gamma[8];
	u8 vreg1out;
	u8 vcom_high;
	u8 vcom_amplitude;
};

static inline struct ili9322 *panel_to_ili9322(struct drm_panel *panel)
{
	return container_of(panel, struct ili9322, panel);
}

static int ili9322_regmap_spi_write(void *context, const void *data,
				    size_t count)
{
	struct device *dev = context;
	struct spi_device *spi = to_spi_device(dev);
	u8 buf[2];

	/* Clear bit 7 to write */
	memcpy(buf, data, 2);
	buf[0] &= ~0x80;

	dev_dbg(dev, "WRITE: %02x %02x\n", buf[0], buf[1]);
	return spi_write_then_read(spi, buf, 2, NULL, 0);
}

static int ili9322_regmap_spi_read(void *context, const void *reg,
				   size_t reg_size, void *val, size_t val_size)
{
	struct device *dev = context;
	struct spi_device *spi = to_spi_device(dev);
	u8 buf[1];

	/* Set bit 7 to 1 to read */
	memcpy(buf, reg, 1);
	dev_dbg(dev, "READ: %02x reg size = %zu, val size = %zu\n",
		buf[0], reg_size, val_size);
	buf[0] |= 0x80;

	return spi_write_then_read(spi, buf, 1, val, 1);
}

static const struct regmap_bus ili9322_regmap_bus = {
	.write = ili9322_regmap_spi_write,
	.read = ili9322_regmap_spi_read,
	.reg_format_endian_default = REGMAP_ENDIAN_BIG,
	.val_format_endian_default = REGMAP_ENDIAN_BIG,
};

static bool ili9322_writeable_reg(struct device *dev, unsigned int reg)
{
	/* Just register 0 is read-only */
	if (reg == 0x00)
		return false;
	return true;
}

static const struct regmap_config ili9322_regmap_config = {
	.reg_bits = 8,
	.val_bits = 8,
	.max_register = 0x44,
	.cache_type = REGCACHE_MAPLE,
	.writeable_reg = ili9322_writeable_reg,

Annotation

Implementation Notes