drivers/gpu/drm/panel/panel-innolux-ej030na.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/panel/panel-innolux-ej030na.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/panel/panel-innolux-ej030na.c- Extension
.c- Size
- 7216 bytes
- Lines
- 310
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/delay.hlinux/device.hlinux/gpio/consumer.hlinux/media-bus-format.hlinux/module.hlinux/of.hlinux/platform_device.hlinux/regmap.hlinux/regulator/consumer.hlinux/spi/spi.hdrm/drm_modes.hdrm/drm_panel.h
Detected Declarations
struct ej030na_infostruct ej030nafunction ej030na_preparefunction ej030na_unpreparefunction ej030na_enablefunction ej030na_disablefunction ej030na_get_modesfunction ej030na_probefunction ej030na_remove
Annotated Snippet
struct ej030na_info {
const struct drm_display_mode *display_modes;
unsigned int num_modes;
u16 width_mm, height_mm;
u32 bus_format, bus_flags;
};
struct ej030na {
struct drm_panel panel;
struct spi_device *spi;
struct regmap *map;
const struct ej030na_info *panel_info;
struct regulator *supply;
struct gpio_desc *reset_gpio;
};
static inline struct ej030na *to_ej030na(struct drm_panel *panel)
{
return container_of(panel, struct ej030na, panel);
}
static const struct reg_sequence ej030na_init_sequence[] = {
{ 0x05, 0x1e },
{ 0x05, 0x5c },
{ 0x02, 0x14 },
{ 0x03, 0x40 },
{ 0x04, 0x07 },
{ 0x06, 0x12 },
{ 0x07, 0xd2 },
{ 0x0c, 0x06 },
{ 0x0d, 0x40 },
{ 0x0e, 0x40 },
{ 0x0f, 0x40 },
{ 0x10, 0x40 },
{ 0x11, 0x40 },
{ 0x2f, 0x40 },
{ 0x5a, 0x02 },
{ 0x30, 0x07 },
{ 0x31, 0x57 },
{ 0x32, 0x53 },
{ 0x33, 0x77 },
{ 0x34, 0xb8 },
{ 0x35, 0xbd },
{ 0x36, 0xb8 },
{ 0x37, 0xe7 },
{ 0x38, 0x04 },
{ 0x39, 0xff },
{ 0x40, 0x0b },
{ 0x41, 0xb8 },
{ 0x42, 0xab },
{ 0x43, 0xb9 },
{ 0x44, 0x6a },
{ 0x45, 0x56 },
{ 0x46, 0x61 },
{ 0x47, 0x08 },
{ 0x48, 0x0f },
{ 0x49, 0x0f },
};
static int ej030na_prepare(struct drm_panel *panel)
{
struct ej030na *priv = to_ej030na(panel);
struct device *dev = &priv->spi->dev;
int err;
err = regulator_enable(priv->supply);
if (err) {
dev_err(dev, "Failed to enable power supply: %d\n", err);
return err;
}
/* Reset the chip */
gpiod_set_value_cansleep(priv->reset_gpio, 1);
usleep_range(50, 150);
gpiod_set_value_cansleep(priv->reset_gpio, 0);
usleep_range(50, 150);
err = regmap_multi_reg_write(priv->map, ej030na_init_sequence,
ARRAY_SIZE(ej030na_init_sequence));
if (err) {
dev_err(dev, "Failed to init registers: %d\n", err);
goto err_disable_regulator;
}
return 0;
Annotation
- Immediate include surface: `linux/delay.h`, `linux/device.h`, `linux/gpio/consumer.h`, `linux/media-bus-format.h`, `linux/module.h`, `linux/of.h`, `linux/platform_device.h`, `linux/regmap.h`.
- Detected declarations: `struct ej030na_info`, `struct ej030na`, `function ej030na_prepare`, `function ej030na_unprepare`, `function ej030na_enable`, `function ej030na_disable`, `function ej030na_get_modes`, `function ej030na_probe`, `function ej030na_remove`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.