drivers/gpu/drm/panel/panel-lg-sw43408.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/panel/panel-lg-sw43408.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/panel/panel-lg-sw43408.c
Extension
.c
Size
8413 bytes
Lines
325
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct sw43408_panel {
	struct drm_panel base;
	struct mipi_dsi_device *link;

	struct regulator_bulk_data *supplies;

	struct gpio_desc *reset_gpio;

	struct drm_dsc_config dsc;
};

static inline struct sw43408_panel *to_panel_info(struct drm_panel *panel)
{
	return container_of(panel, struct sw43408_panel, base);
}

static int sw43408_unprepare(struct drm_panel *panel)
{
	struct sw43408_panel *sw43408 = to_panel_info(panel);
	struct mipi_dsi_multi_context ctx = { .dsi = sw43408->link };
	int ret;

	mipi_dsi_dcs_set_display_off_multi(&ctx);

	mipi_dsi_dcs_enter_sleep_mode_multi(&ctx);

	mipi_dsi_msleep(&ctx, 100);

	gpiod_set_value(sw43408->reset_gpio, 1);

	ret = regulator_bulk_disable(ARRAY_SIZE(sw43408_supplies), sw43408->supplies);

	return ret ? : ctx.accum_err;
}

static int sw43408_program(struct drm_panel *panel)
{
	struct sw43408_panel *sw43408 = to_panel_info(panel);
	struct mipi_dsi_multi_context ctx = { .dsi = sw43408->link };
	struct drm_dsc_picture_parameter_set pps;

	mipi_dsi_dcs_write_seq_multi(&ctx, MIPI_DCS_SET_GAMMA_CURVE, 0x02);

	mipi_dsi_dcs_set_tear_on_multi(&ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);

	mipi_dsi_dcs_write_seq_multi(&ctx, 0x53, 0x0c, 0x30);
	mipi_dsi_dcs_write_seq_multi(&ctx, 0x55, 0x00, 0x70, 0xdf, 0x00, 0x70, 0xdf);
	mipi_dsi_dcs_write_seq_multi(&ctx, 0xf7, 0x01, 0x49, 0x0c);

	mipi_dsi_dcs_exit_sleep_mode_multi(&ctx);

	mipi_dsi_msleep(&ctx, 135);

	/* COMPRESSION_MODE moved after setting the PPS */

	mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0xac);
	mipi_dsi_dcs_write_seq_multi(&ctx, 0xe5,
			       0x00, 0x3a, 0x00, 0x3a, 0x00, 0x0e, 0x10);
	mipi_dsi_dcs_write_seq_multi(&ctx, 0xb5,
			       0x75, 0x60, 0x2d, 0x5d, 0x80, 0x00, 0x0a, 0x0b,
			       0x00, 0x05, 0x0b, 0x00, 0x80, 0x0d, 0x0e, 0x40,
			       0x00, 0x0c, 0x00, 0x16, 0x00, 0xb8, 0x00, 0x80,
			       0x0d, 0x0e, 0x40, 0x00, 0x0c, 0x00, 0x16, 0x00,
			       0xb8, 0x00, 0x81, 0x00, 0x03, 0x03, 0x03, 0x01,
			       0x01);
	mipi_dsi_msleep(&ctx, 85);
	mipi_dsi_dcs_write_seq_multi(&ctx, 0xcd,
			       0x00, 0x00, 0x00, 0x19, 0x19, 0x19, 0x19, 0x19,
			       0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19,
			       0x16, 0x16);
	mipi_dsi_dcs_write_seq_multi(&ctx, 0xcb, 0x80, 0x5c, 0x07, 0x03, 0x28);
	mipi_dsi_dcs_write_seq_multi(&ctx, 0xc0, 0x02, 0x02, 0x0f);
	mipi_dsi_dcs_write_seq_multi(&ctx, 0x55, 0x04, 0x61, 0xdb, 0x04, 0x70, 0xdb);
	mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0xca);

	mipi_dsi_dcs_set_display_on_multi(&ctx);

	mipi_dsi_msleep(&ctx, 50);

	sw43408->link->mode_flags &= ~MIPI_DSI_MODE_LPM;

	drm_dsc_pps_payload_pack(&pps, sw43408->link->dsc);

	mipi_dsi_picture_parameter_set_multi(&ctx, &pps);

	sw43408->link->mode_flags |= MIPI_DSI_MODE_LPM;

	/*
	 * This panel uses PPS selectors with offset:
	 * PPS 1 if pps_identifier is 0

Annotation

Implementation Notes