drivers/gpu/drm/panel/panel-nec-nl8048hl11.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/panel/panel-nec-nl8048hl11.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/panel/panel-nec-nl8048hl11.c
Extension
.c
Size
6296 bytes
Lines
252
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct nl8048_panel {
	struct drm_panel panel;

	struct spi_device *spi;
	struct gpio_desc *reset_gpio;
};

#define to_nl8048_device(p) container_of(p, struct nl8048_panel, panel)

static int nl8048_write(struct nl8048_panel *lcd, unsigned char addr,
			unsigned char value)
{
	u8 data[4] = { value, 0x01, addr, 0x00 };
	int ret;

	ret = spi_write(lcd->spi, data, sizeof(data));
	if (ret)
		dev_err(&lcd->spi->dev, "SPI write to %u failed: %d\n",
			addr, ret);

	return ret;
}

static int nl8048_init(struct nl8048_panel *lcd)
{
	static const struct {
		unsigned char addr;
		unsigned char data;
	} nl8048_init_seq[] = {
		{   3, 0x01 }, {   0, 0x00 }, {   1, 0x01 }, {   4, 0x00 },
		{   5, 0x14 }, {   6, 0x24 }, {  16, 0xd7 }, {  17, 0x00 },
		{  18, 0x00 }, {  19, 0x55 }, {  20, 0x01 }, {  21, 0x70 },
		{  22, 0x1e }, {  23, 0x25 }, {  24, 0x25 }, {  25, 0x02 },
		{  26, 0x02 }, {  27, 0xa0 }, {  32, 0x2f }, {  33, 0x0f },
		{  34, 0x0f }, {  35, 0x0f }, {  36, 0x0f }, {  37, 0x0f },
		{  38, 0x0f }, {  39, 0x00 }, {  40, 0x02 }, {  41, 0x02 },
		{  42, 0x02 }, {  43, 0x0f }, {  44, 0x0f }, {  45, 0x0f },
		{  46, 0x0f }, {  47, 0x0f }, {  48, 0x0f }, {  49, 0x0f },
		{  50, 0x00 }, {  51, 0x02 }, {  52, 0x02 }, {  53, 0x02 },
		{  80, 0x0c }, {  83, 0x42 }, {  84, 0x42 }, {  85, 0x41 },
		{  86, 0x14 }, {  89, 0x88 }, {  90, 0x01 }, {  91, 0x00 },
		{  92, 0x02 }, {  93, 0x0c }, {  94, 0x1c }, {  95, 0x27 },
		{  98, 0x49 }, {  99, 0x27 }, { 102, 0x76 }, { 103, 0x27 },
		{ 112, 0x01 }, { 113, 0x0e }, { 114, 0x02 }, { 115, 0x0c },
		{ 118, 0x0c }, { 121, 0x30 }, { 130, 0x00 }, { 131, 0x00 },
		{ 132, 0xfc }, { 134, 0x00 }, { 136, 0x00 }, { 138, 0x00 },
		{ 139, 0x00 }, { 140, 0x00 }, { 141, 0xfc }, { 143, 0x00 },
		{ 145, 0x00 }, { 147, 0x00 }, { 148, 0x00 }, { 149, 0x00 },
		{ 150, 0xfc }, { 152, 0x00 }, { 154, 0x00 }, { 156, 0x00 },
		{ 157, 0x00 },
	};

	unsigned int i;
	int ret;

	for (i = 0; i < ARRAY_SIZE(nl8048_init_seq); ++i) {
		ret = nl8048_write(lcd, nl8048_init_seq[i].addr,
				   nl8048_init_seq[i].data);
		if (ret < 0)
			return ret;
	}

	udelay(20);

	return nl8048_write(lcd, 2, 0x00);
}

static int nl8048_disable(struct drm_panel *panel)
{
	struct nl8048_panel *lcd = to_nl8048_device(panel);

	gpiod_set_value_cansleep(lcd->reset_gpio, 0);

	return 0;
}

static int nl8048_enable(struct drm_panel *panel)
{
	struct nl8048_panel *lcd = to_nl8048_device(panel);

	gpiod_set_value_cansleep(lcd->reset_gpio, 1);

	return 0;
}

static const struct drm_display_mode nl8048_mode = {
	/*  NEC PIX Clock Ratings MIN:21.8MHz TYP:23.8MHz MAX:25.7MHz */
	.clock	= 23800,
	.hdisplay = 800,
	.hsync_start = 800 + 6,

Annotation

Implementation Notes