drivers/gpu/drm/panel/panel-newvision-nv3052c.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/panel/panel-newvision-nv3052c.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/panel/panel-newvision-nv3052c.c
Extension
.c
Size
17703 bytes
Lines
687
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct nv3052c_reg {
	u8 cmd;
	u8 val;
};

struct nv3052c_panel_info {
	const struct drm_display_mode *display_modes;
	unsigned int num_modes;
	u16 width_mm, height_mm;
	u32 bus_format, bus_flags;
	const struct nv3052c_reg *panel_regs;
	unsigned int panel_regs_len;
};

struct nv3052c {
	struct device *dev;
	struct drm_panel panel;
	struct mipi_dbi dbi;
	const struct nv3052c_panel_info *panel_info;
	struct regulator *supply;
	struct gpio_desc *reset_gpio;
};

/*
 * Common initialization registers for all currently
 * supported displays. Mostly seem to be related
 * to Gamma correction curves and output pad mappings.
 */
static const struct nv3052c_reg common_init_regs[] = {
	// EXTC Command set enable, select page 2
	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 },
	// Set gray scale voltage to adjust gamma
	{ 0xb0, 0x0b }, // PGAMVR0
	{ 0xb1, 0x16 }, // PGAMVR1
	{ 0xb2, 0x17 }, // PGAMVR2
	{ 0xb3, 0x2c }, // PGAMVR3
	{ 0xb4, 0x32 }, // PGAMVR4
	{ 0xb5, 0x3b }, // PGAMVR5
	{ 0xb6, 0x29 }, // PGAMPR0
	{ 0xb7, 0x40 }, // PGAMPR1
	{ 0xb8, 0x0d }, // PGAMPK0
	{ 0xb9, 0x05 }, // PGAMPK1
	{ 0xba, 0x12 }, // PGAMPK2
	{ 0xbb, 0x10 }, // PGAMPK3
	{ 0xbc, 0x12 }, // PGAMPK4
	{ 0xbd, 0x15 }, // PGAMPK5
	{ 0xbe, 0x19 }, // PGAMPK6
	{ 0xbf, 0x0e }, // PGAMPK7
	{ 0xc0, 0x16 }, // PGAMPK8
	{ 0xc1, 0x0a }, // PGAMPK9
	// Set gray scale voltage to adjust gamma
	{ 0xd0, 0x0c }, // NGAMVR0
	{ 0xd1, 0x17 }, // NGAMVR0
	{ 0xd2, 0x14 }, // NGAMVR1
	{ 0xd3, 0x2e }, // NGAMVR2
	{ 0xd4, 0x32 }, // NGAMVR3
	{ 0xd5, 0x3c }, // NGAMVR4
	{ 0xd6, 0x22 }, // NGAMPR0
	{ 0xd7, 0x3d }, // NGAMPR1
	{ 0xd8, 0x0d }, // NGAMPK0
	{ 0xd9, 0x07 }, // NGAMPK1
	{ 0xda, 0x13 }, // NGAMPK2
	{ 0xdb, 0x13 }, // NGAMPK3
	{ 0xdc, 0x11 }, // NGAMPK4
	{ 0xdd, 0x15 }, // NGAMPK5
	{ 0xde, 0x19 }, // NGAMPK6
	{ 0xdf, 0x10 }, // NGAMPK7
	{ 0xe0, 0x17 }, // NGAMPK8
	{ 0xe1, 0x0a }, // NGAMPK9
	// EXTC Command set enable, select page 3
	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 },
	// Set various timing settings
	{ 0x00, 0x2a }, // GIP_VST_1
	{ 0x01, 0x2a }, // GIP_VST_2
	{ 0x02, 0x2a }, // GIP_VST_3
	{ 0x03, 0x2a }, // GIP_VST_4
	{ 0x04, 0x61 }, // GIP_VST_5
	{ 0x05, 0x80 }, // GIP_VST_6
	{ 0x06, 0xc7 }, // GIP_VST_7
	{ 0x07, 0x01 }, // GIP_VST_8
	{ 0x08, 0x03 }, // GIP_VST_9
	{ 0x09, 0x04 }, // GIP_VST_10
	{ 0x70, 0x22 }, // GIP_ECLK1
	{ 0x71, 0x80 }, // GIP_ECLK2
	{ 0x30, 0x2a }, // GIP_CLK_1
	{ 0x31, 0x2a }, // GIP_CLK_2
	{ 0x32, 0x2a }, // GIP_CLK_3
	{ 0x33, 0x2a }, // GIP_CLK_4
	{ 0x34, 0x61 }, // GIP_CLK_5
	{ 0x35, 0xc5 }, // GIP_CLK_6

Annotation

Implementation Notes