drivers/gpu/drm/panel/panel-novatek-nt35532.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/panel/panel-novatek-nt35532.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/panel/panel-novatek-nt35532.c- Extension
.c- Size
- 37652 bytes
- Lines
- 797
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/delay.hlinux/gpio/consumer.hlinux/mod_devicetable.hlinux/module.hlinux/property.hlinux/regulator/consumer.hvideo/mipi_display.hdrm/drm_mipi_dsi.hdrm/drm_modes.hdrm/drm_panel.hdrm/drm_probe_helper.h
Detected Declarations
struct novatek_nt35532struct nt35532_panel_descfunction nt35532_resetfunction rimob_panel_onfunction nt35532_offfunction nt35532_preparefunction nt35532_unpreparefunction nt35532_get_modesfunction nt35532_probefunction nt35532_remove
Annotated Snippet
struct novatek_nt35532 {
struct drm_panel panel;
struct mipi_dsi_device *dsi;
struct regulator_bulk_data *supplies;
struct gpio_desc *reset_gpio;
const struct nt35532_panel_desc *desc;
};
struct nt35532_panel_desc {
const struct drm_display_mode *mode;
int (*on)(struct novatek_nt35532 *ctx);
};
static const struct regulator_bulk_data nt35532_supplies[] = {
{ .supply = "vci" },
{ .supply = "vddi" },
{ .supply = "avee" },
{ .supply = "avdd" },
};
static inline struct novatek_nt35532 *to_novatek_nt35532(struct drm_panel *panel)
{
return container_of_const(panel, struct novatek_nt35532, panel);
}
static void nt35532_reset(struct novatek_nt35532 *ctx)
{
gpiod_set_value_cansleep(ctx->reset_gpio, 0);
usleep_range(10000, 11000);
gpiod_set_value_cansleep(ctx->reset_gpio, 1);
usleep_range(5000, 6000);
gpiod_set_value_cansleep(ctx->reset_gpio, 0);
usleep_range(10000, 11000);
}
static int rimob_panel_on(struct novatek_nt35532 *ctx)
{
struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x01);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6e, 0x80);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x68, 0x13);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x02);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x05);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0x31);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0x7e);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x01);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x01, 0x55);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x04, 0x0c);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x05, 0x3a);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x06, 0x50);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x07, 0xd0);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0a, 0x0f);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0c, 0x06);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0d, 0x6b);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0e, 0x6b);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0f, 0x70);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x10, 0x63);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x11, 0x3c);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x12, 0x5c);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x15, 0x60);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x16, 0x15);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x17, 0x15);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5b, 0xca);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5c, 0x00);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5d, 0x00);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5f, 0x1b);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x60, 0xd5);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x61, 0xf0);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6c, 0xab);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6d, 0x44);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6e, 0x80);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x05);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x00, 0x3f);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x01, 0x3f);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x02, 0x3f);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x03, 0x3f);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x04, 0x38);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x05, 0x3f);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x06, 0x3f);
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x07, 0x19);
Annotation
- Immediate include surface: `linux/delay.h`, `linux/gpio/consumer.h`, `linux/mod_devicetable.h`, `linux/module.h`, `linux/property.h`, `linux/regulator/consumer.h`, `video/mipi_display.h`, `drm/drm_mipi_dsi.h`.
- Detected declarations: `struct novatek_nt35532`, `struct nt35532_panel_desc`, `function nt35532_reset`, `function rimob_panel_on`, `function nt35532_off`, `function nt35532_prepare`, `function nt35532_unprepare`, `function nt35532_get_modes`, `function nt35532_probe`, `function nt35532_remove`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.