drivers/gpu/drm/panel/panel-samsung-s6d27a1.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/panel/panel-samsung-s6d27a1.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/panel/panel-samsung-s6d27a1.c
Extension
.c
Size
8245 bytes
Lines
319
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct s6d27a1 {
	struct device *dev;
	struct mipi_dbi dbi;
	struct drm_panel panel;
	struct gpio_desc *reset;
	struct regulator_bulk_data regulators[2];
};

static const struct drm_display_mode s6d27a1_480_800_mode = {
	/*
	 * The vendor driver states that the S6D27A1 panel
	 * has a pixel clock frequency of 49920000 Hz / 2 = 24960000 Hz.
	 */
	.clock = 24960,
	.hdisplay = 480,
	.hsync_start = 480 + 63,
	.hsync_end = 480 + 63 + 2,
	.htotal = 480 + 63 + 2 + 63,
	.vdisplay = 800,
	.vsync_start = 800 + 11,
	.vsync_end = 800 + 11 + 2,
	.vtotal = 800 + 11 + 2 + 10,
	.width_mm = 50,
	.height_mm = 84,
	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
};

static inline struct s6d27a1 *to_s6d27a1(struct drm_panel *panel)
{
	return container_of(panel, struct s6d27a1, panel);
}

static void s6d27a1_read_mtp_id(struct s6d27a1 *ctx)
{
	struct mipi_dbi *dbi = &ctx->dbi;
	u8 id1, id2, id3;
	int ret;

	ret = mipi_dbi_command_read(dbi, S6D27A1_READID1, &id1);
	if (ret) {
		dev_err(ctx->dev, "unable to read MTP ID 1\n");
		return;
	}
	ret = mipi_dbi_command_read(dbi, S6D27A1_READID2, &id2);
	if (ret) {
		dev_err(ctx->dev, "unable to read MTP ID 2\n");
		return;
	}
	ret = mipi_dbi_command_read(dbi, S6D27A1_READID3, &id3);
	if (ret) {
		dev_err(ctx->dev, "unable to read MTP ID 3\n");
		return;
	}
	dev_info(ctx->dev, "MTP ID: %02x %02x %02x\n", id1, id2, id3);
}

static int s6d27a1_power_on(struct s6d27a1 *ctx)
{
	struct mipi_dbi *dbi = &ctx->dbi;
	int ret;

	/* Power up */
	ret = regulator_bulk_enable(ARRAY_SIZE(ctx->regulators),
				    ctx->regulators);
	if (ret) {
		dev_err(ctx->dev, "failed to enable regulators: %d\n", ret);
		return ret;
	}

	msleep(20);

	/* Assert reset >=1 ms */
	gpiod_set_value_cansleep(ctx->reset, 1);
	usleep_range(1000, 5000);
	/* De-assert reset */
	gpiod_set_value_cansleep(ctx->reset, 0);
	/* Wait >= 10 ms */
	msleep(20);

	/*
	 * Exit sleep mode and initialize display - some hammering is
	 * necessary.
	 */
	mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
	mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
	msleep(120);

	/* Magic to unlock level 2 control of the display */
	mipi_dbi_command(dbi, S6D27A1_PASSWD_L2, 0x5A, 0x5A);

Annotation

Implementation Notes