drivers/gpu/drm/panel/panel-sitronix-st7703.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/panel/panel-sitronix-st7703.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/panel/panel-sitronix-st7703.c
Extension
.c
Size
35087 bytes
Lines
941
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct st7703 {
	struct device *dev;
	struct drm_panel panel;
	struct gpio_desc *reset_gpio;
	struct regulator *vcc;
	struct regulator *iovcc;

	struct dentry *debugfs;
	const struct st7703_panel_desc *desc;
	enum drm_panel_orientation orientation;
};

struct st7703_panel_desc {
	const struct drm_display_mode *mode;
	unsigned int lanes;
	unsigned long mode_flags;
	enum mipi_dsi_pixel_format format;
	void (*init_sequence)(struct mipi_dsi_multi_context *dsi_ctx);
};

static inline struct st7703 *panel_to_st7703(struct drm_panel *panel)
{
	return container_of(panel, struct st7703, panel);
}

static void jh057n_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
{
	/*
	 * Init sequence was supplied by the panel vendor. Most of the commands
	 * resemble the ST7703 but the number of parameters often don't match
	 * so it's likely a clone.
	 */
	mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC,
					 0xF1, 0x12, 0x83);
	mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF,
					 0x10, 0x10, 0x05, 0x05, 0x03, 0xFF, 0x00, 0x00,
					 0x00, 0x00);
	mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR,
					 0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70,
					 0x00);
	mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x4E);
	mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0B);
	mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80);
	mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30);
	mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ,
					 0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00,
					 0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10);
	mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x08, 0x08);
	mipi_dsi_msleep(dsi_ctx, 20);

	mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x3F, 0x3F);
	mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
	mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1,
					 0x82, 0x10, 0x06, 0x05, 0x9E, 0x0A, 0xA5, 0x12,
					 0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38,
					 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00,
					 0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88,
					 0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64,
					 0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
					 0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
					 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
	mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2,
					 0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
					 0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88,
					 0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13,
					 0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
					 0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00,
					 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
					 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0A,
					 0xA5, 0x00, 0x00, 0x00, 0x00);
	mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA,
					 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, 0x37,
					 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, 0x11,
					 0x18, 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41,
					 0x37, 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10,
					 0x11, 0x18);
	mipi_dsi_msleep(dsi_ctx, 20);
}

static const struct drm_display_mode jh057n00900_mode = {
	.hdisplay    = 720,
	.hsync_start = 720 + 90,
	.hsync_end   = 720 + 90 + 20,
	.htotal	     = 720 + 90 + 20 + 20,
	.vdisplay    = 1440,
	.vsync_start = 1440 + 20,
	.vsync_end   = 1440 + 20 + 4,
	.vtotal	     = 1440 + 20 + 4 + 12,
	.clock	     = 75276,
	.flags	     = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,

Annotation

Implementation Notes