drivers/gpu/drm/panel/panel-tpo-td028ttec1.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/panel/panel-tpo-td028ttec1.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/panel/panel-tpo-td028ttec1.c- Extension
.c- Size
- 10411 bytes
- Lines
- 388
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/delay.hlinux/module.hlinux/spi/spi.hdrm/drm_connector.hdrm/drm_modes.hdrm/drm_panel.h
Detected Declarations
struct td028ttec1_panelfunction jbt_ret_write_0function jbt_reg_write_1function jbt_reg_write_2function td028ttec1_preparefunction td028ttec1_enablefunction td028ttec1_disablefunction td028ttec1_unpreparefunction td028ttec1_get_modesfunction td028ttec1_probefunction td028ttec1_remove
Annotated Snippet
struct td028ttec1_panel {
struct drm_panel panel;
struct spi_device *spi;
};
#define to_td028ttec1_device(p) container_of(p, struct td028ttec1_panel, panel)
static int
jbt_ret_write_0(struct td028ttec1_panel *lcd, u8 reg, int *err)
{
struct spi_device *spi = lcd->spi;
u16 tx_buf = JBT_COMMAND | reg;
int ret;
if (err && *err)
return *err;
ret = spi_write(spi, (u8 *)&tx_buf, sizeof(tx_buf));
if (ret < 0) {
dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
if (err)
*err = ret;
}
return ret;
}
static int noinline_for_stack
jbt_reg_write_1(struct td028ttec1_panel *lcd,
u8 reg, u8 data, int *err)
{
struct spi_device *spi = lcd->spi;
u16 tx_buf[2];
int ret;
if (err && *err)
return *err;
tx_buf[0] = JBT_COMMAND | reg;
tx_buf[1] = JBT_DATA | data;
ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
if (ret < 0) {
dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
if (err)
*err = ret;
}
return ret;
}
static int noinline_for_stack
jbt_reg_write_2(struct td028ttec1_panel *lcd,
u8 reg, u16 data, int *err)
{
struct spi_device *spi = lcd->spi;
u16 tx_buf[3];
int ret;
if (err && *err)
return *err;
tx_buf[0] = JBT_COMMAND | reg;
tx_buf[1] = JBT_DATA | (data >> 8);
tx_buf[2] = JBT_DATA | (data & 0xff);
ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
if (ret < 0) {
dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
if (err)
*err = ret;
}
return ret;
}
static int td028ttec1_prepare(struct drm_panel *panel)
{
struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
unsigned int i;
int ret = 0;
/* Three times command zero */
for (i = 0; i < 3; ++i) {
jbt_ret_write_0(lcd, 0x00, &ret);
usleep_range(1000, 2000);
}
/* deep standby out */
Annotation
- Immediate include surface: `linux/delay.h`, `linux/module.h`, `linux/spi/spi.h`, `drm/drm_connector.h`, `drm/drm_modes.h`, `drm/drm_panel.h`.
- Detected declarations: `struct td028ttec1_panel`, `function jbt_ret_write_0`, `function jbt_reg_write_1`, `function jbt_reg_write_2`, `function td028ttec1_prepare`, `function td028ttec1_enable`, `function td028ttec1_disable`, `function td028ttec1_unprepare`, `function td028ttec1_get_modes`, `function td028ttec1_probe`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.