drivers/gpu/drm/radeon/cik.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/radeon/cik.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/radeon/cik.c- Extension
.c- Size
- 285816 bytes
- Lines
- 9808
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/firmware.hlinux/module.hlinux/pci.hlinux/slab.hdrm/drm_vblank.hatom.hevergreen.hcik_blit_shaders.hcik.hcikd.hclearstate_ci.hr600.hradeon.hradeon_asic.hradeon_audio.hradeon_ucode.hsi.hvce.h
Detected Declarations
struct hqd_registersstruct bonaire_mqdstruct kv_reset_save_regsstruct dce8_wm_paramsfunction cik_get_allowed_info_registerfunction cik_didt_rregfunction cik_didt_wregfunction ci_get_tempfunction kv_get_tempfunction cik_pciep_rregfunction cik_pciep_wregfunction cik_init_golden_registersfunction cik_get_xclkfunction indexfunction indexfunction cik_srbm_selectfunction hwfunction driverfunction parametersfunction SHsfunction maskfunction RBsfunction cik_setup_rbfunction cik_gpu_initfunction asicsfunction cik_ring_testfunction cik_hdp_flush_cp_ring_emitfunction cik_fence_gfx_ring_emitfunction cik_fence_compute_ring_emitfunction cik_semaphore_ring_emitfunction enginefunction DEfunction ringfunction Enginefunction cik_cp_gfx_load_microcodefunction cik_cp_gfx_startfunction cik_cp_gfx_finifunction cik_cp_gfx_resumefunction cik_gfx_get_rptrfunction cik_gfx_get_wptrfunction cik_gfx_set_wptrfunction cik_compute_get_rptrfunction cik_compute_get_wptrfunction cik_compute_set_wptrfunction cik_compute_stopfunction cik_cp_compute_enablefunction cik_cp_compute_load_microcodefunction cik_cp_compute_start
Annotated Snippet
struct kv_reset_save_regs {
u32 gmcon_reng_execute;
u32 gmcon_misc;
u32 gmcon_misc3;
};
static void kv_save_regs_for_reset(struct radeon_device *rdev,
struct kv_reset_save_regs *save)
{
save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE);
save->gmcon_misc = RREG32(GMCON_MISC);
save->gmcon_misc3 = RREG32(GMCON_MISC3);
WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP);
WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE |
STCTRL_STUTTER_EN));
}
static void kv_restore_regs_for_reset(struct radeon_device *rdev,
struct kv_reset_save_regs *save)
{
int i;
WREG32(GMCON_PGFSM_WRITE, 0);
WREG32(GMCON_PGFSM_CONFIG, 0x200010ff);
for (i = 0; i < 5; i++)
WREG32(GMCON_PGFSM_WRITE, 0);
WREG32(GMCON_PGFSM_WRITE, 0);
WREG32(GMCON_PGFSM_CONFIG, 0x300010ff);
for (i = 0; i < 5; i++)
WREG32(GMCON_PGFSM_WRITE, 0);
WREG32(GMCON_PGFSM_WRITE, 0x210000);
WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff);
for (i = 0; i < 5; i++)
WREG32(GMCON_PGFSM_WRITE, 0);
WREG32(GMCON_PGFSM_WRITE, 0x21003);
WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff);
for (i = 0; i < 5; i++)
WREG32(GMCON_PGFSM_WRITE, 0);
WREG32(GMCON_PGFSM_WRITE, 0x2b00);
WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff);
for (i = 0; i < 5; i++)
WREG32(GMCON_PGFSM_WRITE, 0);
WREG32(GMCON_PGFSM_WRITE, 0);
WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff);
for (i = 0; i < 5; i++)
WREG32(GMCON_PGFSM_WRITE, 0);
WREG32(GMCON_PGFSM_WRITE, 0x420000);
WREG32(GMCON_PGFSM_CONFIG, 0x100010ff);
for (i = 0; i < 5; i++)
WREG32(GMCON_PGFSM_WRITE, 0);
WREG32(GMCON_PGFSM_WRITE, 0x120202);
WREG32(GMCON_PGFSM_CONFIG, 0x500010ff);
for (i = 0; i < 5; i++)
WREG32(GMCON_PGFSM_WRITE, 0);
WREG32(GMCON_PGFSM_WRITE, 0x3e3e36);
WREG32(GMCON_PGFSM_CONFIG, 0x600010ff);
for (i = 0; i < 5; i++)
WREG32(GMCON_PGFSM_WRITE, 0);
WREG32(GMCON_PGFSM_WRITE, 0x373f3e);
WREG32(GMCON_PGFSM_CONFIG, 0x700010ff);
for (i = 0; i < 5; i++)
WREG32(GMCON_PGFSM_WRITE, 0);
WREG32(GMCON_PGFSM_WRITE, 0x3e1332);
WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff);
WREG32(GMCON_MISC3, save->gmcon_misc3);
WREG32(GMCON_MISC, save->gmcon_misc);
WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute);
}
Annotation
- Immediate include surface: `linux/firmware.h`, `linux/module.h`, `linux/pci.h`, `linux/slab.h`, `drm/drm_vblank.h`, `atom.h`, `evergreen.h`, `cik_blit_shaders.h`.
- Detected declarations: `struct hqd_registers`, `struct bonaire_mqd`, `struct kv_reset_save_regs`, `struct dce8_wm_params`, `function cik_get_allowed_info_register`, `function cik_didt_rreg`, `function cik_didt_wreg`, `function ci_get_temp`, `function kv_get_temp`, `function cik_pciep_rreg`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.