drivers/gpu/drm/radeon/cikd.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/radeon/cikd.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/radeon/cikd.h
Extension
.h
Size
93219 bytes
Lines
2173
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef CIK_H
#define CIK_H

#define BONAIRE_GB_ADDR_CONFIG_GOLDEN        0x12010001
#define HAWAII_GB_ADDR_CONFIG_GOLDEN         0x12011003

#define CIK_RB_BITMAP_WIDTH_PER_SH     2
#define HAWAII_RB_BITMAP_WIDTH_PER_SH  4

/* DIDT IND registers */
#define DIDT_SQ_CTRL0                                     0x0
#       define DIDT_CTRL_EN                               (1 << 0)
#define DIDT_DB_CTRL0                                     0x20
#define DIDT_TD_CTRL0                                     0x40
#define DIDT_TCP_CTRL0                                    0x60

/* SMC IND registers */
#define DPM_TABLE_475                                     0x3F768
#       define SamuBootLevel(x)                           ((x) << 0)
#       define SamuBootLevel_MASK                         0x000000ff
#       define SamuBootLevel_SHIFT                        0
#       define AcpBootLevel(x)                            ((x) << 8)
#       define AcpBootLevel_MASK                          0x0000ff00
#       define AcpBootLevel_SHIFT                         8
#       define VceBootLevel(x)                            ((x) << 16)
#       define VceBootLevel_MASK                          0x00ff0000
#       define VceBootLevel_SHIFT                         16
#       define UvdBootLevel(x)                            ((x) << 24)
#       define UvdBootLevel_MASK                          0xff000000
#       define UvdBootLevel_SHIFT                         24

#define FIRMWARE_FLAGS                                    0x3F800
#       define INTERRUPTS_ENABLED                         (1 << 0)

#define NB_DPM_CONFIG_1                                   0x3F9E8
#       define Dpm0PgNbPsLo(x)                            ((x) << 0)
#       define Dpm0PgNbPsLo_MASK                          0x000000ff
#       define Dpm0PgNbPsLo_SHIFT                         0
#       define Dpm0PgNbPsHi(x)                            ((x) << 8)
#       define Dpm0PgNbPsHi_MASK                          0x0000ff00
#       define Dpm0PgNbPsHi_SHIFT                         8
#       define DpmXNbPsLo(x)                              ((x) << 16)
#       define DpmXNbPsLo_MASK                            0x00ff0000
#       define DpmXNbPsLo_SHIFT                           16
#       define DpmXNbPsHi(x)                              ((x) << 24)
#       define DpmXNbPsHi_MASK                            0xff000000
#       define DpmXNbPsHi_SHIFT                           24

#define	SMC_SYSCON_RESET_CNTL				0x80000000
#       define RST_REG                                  (1 << 0)
#define	SMC_SYSCON_CLOCK_CNTL_0				0x80000004
#       define CK_DISABLE                               (1 << 0)
#       define CKEN                                     (1 << 24)

#define	SMC_SYSCON_MISC_CNTL				0x80000010

#define SMC_SYSCON_MSG_ARG_0                              0x80000068

#define SMC_PC_C                                          0x80000370

#define SMC_SCRATCH9                                      0x80000424

#define RCU_UC_EVENTS                                     0xC0000004
#       define BOOT_SEQ_DONE                              (1 << 7)

#define GENERAL_PWRMGT                                    0xC0200000
#       define GLOBAL_PWRMGT_EN                           (1 << 0)
#       define STATIC_PM_EN                               (1 << 1)
#       define THERMAL_PROTECTION_DIS                     (1 << 2)
#       define THERMAL_PROTECTION_TYPE                    (1 << 3)
#       define SW_SMIO_INDEX(x)                           ((x) << 6)
#       define SW_SMIO_INDEX_MASK                         (1 << 6)
#       define SW_SMIO_INDEX_SHIFT                        6
#       define VOLT_PWRMGT_EN                             (1 << 10)
#       define GPU_COUNTER_CLK                            (1 << 15)
#       define DYN_SPREAD_SPECTRUM_EN                     (1 << 23)

#define CNB_PWRMGT_CNTL                                   0xC0200004
#       define GNB_SLOW_MODE(x)                           ((x) << 0)
#       define GNB_SLOW_MODE_MASK                         (3 << 0)
#       define GNB_SLOW_MODE_SHIFT                        0
#       define GNB_SLOW                                   (1 << 2)
#       define FORCE_NB_PS1                               (1 << 3)
#       define DPM_ENABLED                                (1 << 4)

#define SCLK_PWRMGT_CNTL                                  0xC0200008
#       define SCLK_PWRMGT_OFF                            (1 << 0)
#       define RESET_BUSY_CNT                             (1 << 4)
#       define RESET_SCLK_CNT                             (1 << 5)
#       define DYNAMIC_PM_EN                              (1 << 21)

Annotation

Implementation Notes