drivers/gpu/drm/radeon/evergreen.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/radeon/evergreen.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/radeon/evergreen.c- Extension
.c- Size
- 165686 bytes
- Lines
- 5547
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/firmware.hlinux/pci.hlinux/slab.hdrm/drm_edid.hdrm/drm_vblank.hdrm/radeon_drm.hdrm/drm_fourcc.hdrm/drm_framebuffer.hatom.havivod.hcik.hni.hrv770.hevergreen.hevergreen_blit_shaders.hevergreen_reg.hevergreend.hradeon.hradeon_asic.hradeon_audio.hradeon_ucode.hsi.hclearstate_evergreen.h
Detected Declarations
struct evergreen_wm_paramsfunction filesfunction eg_cg_wregfunction eg_pif_phy0_rregfunction eg_pif_phy0_wregfunction eg_pif_phy1_rregfunction eg_pif_phy1_wregfunction evergreen_init_golden_registersfunction evergreen_get_allowed_info_registerfunction evergreen_tiling_fieldsfunction sumo_set_uvd_clockfunction sumo_set_uvd_clocksfunction evergreen_set_uvd_clocksfunction evergreen_fix_pci_max_read_req_sizefunction dce4_program_fmtfunction dce4_is_in_vblankfunction dce4_is_counter_movingfunction crtcfunction addressfunction evergreen_page_flip_pendingfunction evergreen_get_tempfunction sumo_get_tempfunction sumo_pm_init_profilefunction btc_pm_init_profilefunction evergreen_pm_miscfunction changefunction changefunction connectedfunction pinfunction cardfunction list_for_each_entryfunction cardfunction list_for_each_entryfunction evergreen_line_buffer_adjustfunction evergreen_get_number_of_dram_channelsfunction evergreen_dram_bandwidthfunction evergreen_dram_bandwidth_for_displayfunction evergreen_data_return_bandwidthfunction evergreen_dmif_request_bandwidthfunction evergreen_available_bandwidthfunction evergreen_average_bandwidthfunction evergreen_latency_watermarkfunction evergreen_average_bandwidth_vs_dram_bandwidth_for_displayfunction evergreen_average_bandwidth_vs_available_bandwidthfunction evergreen_check_latency_hidingfunction evergreen_program_watermarksfunction modefunction MC
Annotated Snippet
struct evergreen_wm_params {
u32 dram_channels; /* number of dram channels */
u32 yclk; /* bandwidth per dram data pin in kHz */
u32 sclk; /* engine clock in kHz */
u32 disp_clk; /* display clock in kHz */
u32 src_width; /* viewport width */
u32 active_time; /* active display time in ns */
u32 blank_time; /* blank time in ns */
bool interlaced; /* mode is interlaced */
fixed20_12 vsc; /* vertical scale ratio */
u32 num_heads; /* number of active crtcs */
u32 bytes_per_pixel; /* bytes per pixel display + overlay */
u32 lb_size; /* line buffer allocated to pipe */
u32 vtaps; /* vertical scaler taps */
};
static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
{
/* Calculate DRAM Bandwidth and the part allocated to display. */
fixed20_12 dram_efficiency; /* 0.7 */
fixed20_12 yclk, dram_channels, bandwidth;
fixed20_12 a;
a.full = dfixed_const(1000);
yclk.full = dfixed_const(wm->yclk);
yclk.full = dfixed_div(yclk, a);
dram_channels.full = dfixed_const(wm->dram_channels * 4);
a.full = dfixed_const(10);
dram_efficiency.full = dfixed_const(7);
dram_efficiency.full = dfixed_div(dram_efficiency, a);
bandwidth.full = dfixed_mul(dram_channels, yclk);
bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
return dfixed_trunc(bandwidth);
}
static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
{
/* Calculate DRAM Bandwidth and the part allocated to display. */
fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
fixed20_12 yclk, dram_channels, bandwidth;
fixed20_12 a;
a.full = dfixed_const(1000);
yclk.full = dfixed_const(wm->yclk);
yclk.full = dfixed_div(yclk, a);
dram_channels.full = dfixed_const(wm->dram_channels * 4);
a.full = dfixed_const(10);
disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
bandwidth.full = dfixed_mul(dram_channels, yclk);
bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
return dfixed_trunc(bandwidth);
}
static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
{
/* Calculate the display Data return Bandwidth */
fixed20_12 return_efficiency; /* 0.8 */
fixed20_12 sclk, bandwidth;
fixed20_12 a;
a.full = dfixed_const(1000);
sclk.full = dfixed_const(wm->sclk);
sclk.full = dfixed_div(sclk, a);
a.full = dfixed_const(10);
return_efficiency.full = dfixed_const(8);
return_efficiency.full = dfixed_div(return_efficiency, a);
a.full = dfixed_const(32);
bandwidth.full = dfixed_mul(a, sclk);
bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
return dfixed_trunc(bandwidth);
}
static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
{
/* Calculate the DMIF Request Bandwidth */
fixed20_12 disp_clk_request_efficiency; /* 0.8 */
fixed20_12 disp_clk, bandwidth;
fixed20_12 a;
a.full = dfixed_const(1000);
disp_clk.full = dfixed_const(wm->disp_clk);
disp_clk.full = dfixed_div(disp_clk, a);
a.full = dfixed_const(10);
disp_clk_request_efficiency.full = dfixed_const(8);
disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
a.full = dfixed_const(32);
Annotation
- Immediate include surface: `linux/firmware.h`, `linux/pci.h`, `linux/slab.h`, `drm/drm_edid.h`, `drm/drm_vblank.h`, `drm/radeon_drm.h`, `drm/drm_fourcc.h`, `drm/drm_framebuffer.h`.
- Detected declarations: `struct evergreen_wm_params`, `function files`, `function eg_cg_wreg`, `function eg_pif_phy0_rreg`, `function eg_pif_phy0_wreg`, `function eg_pif_phy1_rreg`, `function eg_pif_phy1_wreg`, `function evergreen_init_golden_registers`, `function evergreen_get_allowed_info_register`, `function evergreen_tiling_fields`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.