drivers/gpu/drm/radeon/kv_dpm.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/radeon/kv_dpm.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/radeon/kv_dpm.h
Extension
.h
Size
5315 bytes
Lines
201
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct kv_pt_config_reg {
	u32 offset;
	u32 mask;
	u32 shift;
	u32 value;
	enum kv_pt_config_reg_type type;
};

struct kv_lcac_config_values {
	u32 block_id;
	u32 signal_id;
	u32 t;
};

struct kv_lcac_config_reg {
	u32 cntl;
	u32 block_mask;
	u32 block_shift;
	u32 signal_mask;
	u32 signal_shift;
	u32 t_mask;
	u32 t_shift;
	u32 enable_mask;
	u32 enable_shift;
};

struct kv_pl {
	u32 sclk;
	u8 vddc_index;
	u8 ds_divider_index;
	u8 ss_divider_index;
	u8 allow_gnb_slow;
	u8 force_nbp_state;
	u8 display_wm;
	u8 vce_wm;
};

struct kv_ps {
	struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
	u32 num_levels;
	bool need_dfs_bypass;
	u8 dpm0_pg_nb_ps_lo;
	u8 dpm0_pg_nb_ps_hi;
	u8 dpmx_nb_ps_lo;
	u8 dpmx_nb_ps_hi;
};

struct kv_sys_info {
	u32 bootup_uma_clk;
	u32 bootup_sclk;
	u32 dentist_vco_freq;
	u32 nb_dpm_enable;
	u32 nbp_memory_clock[KV_NUM_NBPSTATES];
	u32 nbp_n_clock[KV_NUM_NBPSTATES];
	u16 bootup_nb_voltage_index;
	u8 htc_tmp_lmt;
	u8 htc_hyst_lmt;
	struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
	struct sumo_vid_mapping_table vid_mapping_table;
	u32 uma_channel_number;
};

struct kv_power_info {
	u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];
	u32 voltage_drop_t;
	struct kv_sys_info sys_info;
	struct kv_pl boot_pl;
	bool enable_nb_ps_policy;
	bool disable_nb_ps3_in_battery;
	bool video_start;
	bool battery_state;
	u32 lowest_valid;
	u32 highest_valid;
	u16 high_voltage_t;
	bool cac_enabled;
	bool bapm_enable;
	/* smc offsets */
	u32 sram_end;
	u32 dpm_table_start;
	u32 soft_regs_start;
	/* dpm SMU tables */
	u8 graphics_dpm_level_count;
	u8 uvd_level_count;
	u8 vce_level_count;
	u8 acp_level_count;
	u8 samu_level_count;
	u16 fps_high_t;
	SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
	SMU7_Fusion_ACPILevel acpi_level;
	SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD];

Annotation

Implementation Notes