drivers/gpu/drm/radeon/r600.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/radeon/r600.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/radeon/r600.c- Extension
.c- Size
- 138395 bytes
- Lines
- 4618
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/debugfs.hlinux/firmware.hlinux/module.hlinux/pci.hlinux/seq_file.hlinux/slab.hdrm/drm_device.hdrm/drm_vblank.hdrm/radeon_drm.hatom.havivod.hevergreen.hr600.hr600d.hrv770.hradeon.hradeon_asic.hradeon_audio.hradeon_mode.hradeon_ucode.h
Detected Declarations
function r600_rcu_rregfunction r600_rcu_wregfunction r600_uvd_ctx_rregfunction r600_uvd_ctx_wregfunction r600_get_allowed_info_registerfunction r600_get_xclkfunction r600_set_uvd_clocksfunction dce3_program_fmtfunction rv6xx_get_tempfunction r600_pm_get_dynpm_statefunction rs780_pm_init_profilefunction r600_pm_init_profilefunction r600_pm_miscfunction r600_gui_idlefunction r600_hpd_sensefunction r600_hpd_set_polarityfunction r600_hpd_initfunction list_for_each_entryfunction r600_hpd_finifunction list_for_each_entryfunction r600_pcie_gart_tlb_flushfunction r600_pcie_gart_initfunction r600_pcie_gart_enablefunction r600_pcie_gart_disablefunction r600_pcie_gart_finifunction r600_agp_enablefunction r600_mc_wait_for_idlefunction rs780_mc_rregfunction rs780_mc_wregfunction r600_mc_programfunction CPUfunction r600_mc_initfunction r600_vram_scratch_initfunction r600_vram_scratch_finifunction r600_set_bios_scratch_engine_hungfunction r600_print_gpu_status_regsfunction r600_is_display_hungfunction r600_gpu_check_soft_resetfunction r600_gpu_soft_resetfunction r600_gpu_pci_config_resetfunction r600_asic_resetfunction r600_gfx_is_lockupfunction r6xx_remap_render_backendfunction r600_count_pipe_bitsfunction r600_gpu_initfunction r600_pciep_rregfunction r600_pciep_wregfunction r600_cp_stop
Annotated Snippet
switch (rdev->pm.dynpm_planned_action) {
case DYNPM_ACTION_MINIMUM:
rdev->pm.requested_power_state_index = min_power_state_index;
rdev->pm.requested_clock_mode_index = 0;
rdev->pm.dynpm_can_downclock = false;
break;
case DYNPM_ACTION_DOWNCLOCK:
if (rdev->pm.current_power_state_index == min_power_state_index) {
rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
rdev->pm.dynpm_can_downclock = false;
} else {
if (rdev->pm.active_crtc_count > 1) {
for (i = 0; i < rdev->pm.num_power_states; i++) {
if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
continue;
else if (i >= rdev->pm.current_power_state_index) {
rdev->pm.requested_power_state_index =
rdev->pm.current_power_state_index;
break;
} else {
rdev->pm.requested_power_state_index = i;
break;
}
}
} else {
if (rdev->pm.current_power_state_index == 0)
rdev->pm.requested_power_state_index =
rdev->pm.num_power_states - 1;
else
rdev->pm.requested_power_state_index =
rdev->pm.current_power_state_index - 1;
}
}
rdev->pm.requested_clock_mode_index = 0;
/* don't use the power state if crtcs are active and no display flag is set */
if ((rdev->pm.active_crtc_count > 0) &&
(rdev->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].flags &
RADEON_PM_MODE_NO_DISPLAY)) {
rdev->pm.requested_power_state_index++;
}
break;
case DYNPM_ACTION_UPCLOCK:
if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
rdev->pm.dynpm_can_upclock = false;
} else {
if (rdev->pm.active_crtc_count > 1) {
for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
continue;
else if (i <= rdev->pm.current_power_state_index) {
rdev->pm.requested_power_state_index =
rdev->pm.current_power_state_index;
break;
} else {
rdev->pm.requested_power_state_index = i;
break;
}
}
} else
rdev->pm.requested_power_state_index =
rdev->pm.current_power_state_index + 1;
}
rdev->pm.requested_clock_mode_index = 0;
break;
case DYNPM_ACTION_DEFAULT:
rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
rdev->pm.requested_clock_mode_index = 0;
rdev->pm.dynpm_can_upclock = false;
break;
case DYNPM_ACTION_NONE:
default:
DRM_ERROR("Requested mode for not defined action\n");
return;
}
} else {
/* XXX select a power state based on AC/DC, single/dualhead, etc. */
/* for now just select the first power state and switch between clock modes */
/* power state array is low to high, default is first (0) */
if (rdev->pm.active_crtc_count > 1) {
rdev->pm.requested_power_state_index = -1;
/* start at 1 as we don't want the default mode */
for (i = 1; i < rdev->pm.num_power_states; i++) {
if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
continue;
else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
(rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
rdev->pm.requested_power_state_index = i;
break;
Annotation
- Immediate include surface: `linux/debugfs.h`, `linux/firmware.h`, `linux/module.h`, `linux/pci.h`, `linux/seq_file.h`, `linux/slab.h`, `drm/drm_device.h`, `drm/drm_vblank.h`.
- Detected declarations: `function r600_rcu_rreg`, `function r600_rcu_wreg`, `function r600_uvd_ctx_rreg`, `function r600_uvd_ctx_wreg`, `function r600_get_allowed_info_register`, `function r600_get_xclk`, `function r600_set_uvd_clocks`, `function dce3_program_fmt`, `function rv6xx_get_temp`, `function r600_pm_get_dynpm_state`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.