drivers/gpu/drm/radeon/r600_reg.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/radeon/r600_reg.h

Extension

.h

Size

8618 bytes

Lines

202

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __R600_REG_H__
#define __R600_REG_H__

#define R600_PCIE_PORT_INDEX                0x0038
#define R600_PCIE_PORT_DATA                 0x003c

#define R600_RCU_INDEX                      0x0100
#define R600_RCU_DATA                       0x0104

#define R600_UVD_CTX_INDEX                  0xf4a0
#define R600_UVD_CTX_DATA                   0xf4a4

#define R600_MC_VM_FB_LOCATION			0x2180
#define		R600_MC_FB_BASE_MASK			0x0000FFFF
#define		R600_MC_FB_BASE_SHIFT			0
#define		R600_MC_FB_TOP_MASK			0xFFFF0000
#define		R600_MC_FB_TOP_SHIFT			16
#define R600_MC_VM_AGP_TOP			0x2184
#define		R600_MC_AGP_TOP_MASK			0x0003FFFF
#define		R600_MC_AGP_TOP_SHIFT			0
#define R600_MC_VM_AGP_BOT			0x2188
#define		R600_MC_AGP_BOT_MASK			0x0003FFFF
#define		R600_MC_AGP_BOT_SHIFT			0
#define R600_MC_VM_AGP_BASE			0x218c
#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR	0x2190
#define		R600_LOGICAL_PAGE_NUMBER_MASK		0x000FFFFF
#define		R600_LOGICAL_PAGE_NUMBER_SHIFT		0
#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR	0x2194
#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR	0x2198

#define R700_MC_VM_FB_LOCATION			0x2024
#define		R700_MC_FB_BASE_MASK			0x0000FFFF
#define		R700_MC_FB_BASE_SHIFT			0
#define		R700_MC_FB_TOP_MASK			0xFFFF0000
#define		R700_MC_FB_TOP_SHIFT			16
#define R700_MC_VM_AGP_TOP			0x2028
#define		R700_MC_AGP_TOP_MASK			0x0003FFFF
#define		R700_MC_AGP_TOP_SHIFT			0
#define R700_MC_VM_AGP_BOT			0x202c
#define		R700_MC_AGP_BOT_MASK			0x0003FFFF
#define		R700_MC_AGP_BOT_SHIFT			0
#define R700_MC_VM_AGP_BASE			0x2030
#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR	0x2034
#define		R700_LOGICAL_PAGE_NUMBER_MASK		0x000FFFFF
#define		R700_LOGICAL_PAGE_NUMBER_SHIFT		0
#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR	0x2038
#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR	0x203c

#define R600_RAMCFG				       0x2408
#       define R600_CHANSIZE                           (1 << 7)
#       define R600_CHANSIZE_OVERRIDE                  (1 << 10)


#define R600_GENERAL_PWRMGT                                        0x618
#	define R600_OPEN_DRAIN_PADS				   (1 << 11)

#define R600_LOWER_GPIO_ENABLE                                     0x710
#define R600_CTXSW_VID_LOWER_GPIO_CNTL                             0x718
#define R600_HIGH_VID_LOWER_GPIO_CNTL                              0x71c
#define R600_MEDIUM_VID_LOWER_GPIO_CNTL                            0x720
#define R600_LOW_VID_LOWER_GPIO_CNTL                               0x724

#define R600_D1GRPH_SWAP_CONTROL                     0x610C
#       define R600_D1GRPH_ENDIAN_SWAP(x)            (((x) & 0x3) << 0)
#       define R600_D1GRPH_SWAP_ENDIAN_NONE          0
#       define R600_D1GRPH_SWAP_ENDIAN_16BIT         1
#       define R600_D1GRPH_SWAP_ENDIAN_32BIT         2
#       define R600_D1GRPH_SWAP_ENDIAN_64BIT         3
#       define R600_D1GRPH_RED_CROSSBAR(x)           (((x) & 0x3) << 4)
#       define R600_D1GRPH_RED_SEL_R                 0
#       define R600_D1GRPH_RED_SEL_G                 1
#       define R600_D1GRPH_RED_SEL_B                 2
#       define R600_D1GRPH_RED_SEL_A                 3
#       define R600_D1GRPH_GREEN_CROSSBAR(x)         (((x) & 0x3) << 6)
#       define R600_D1GRPH_GREEN_SEL_G               0
#       define R600_D1GRPH_GREEN_SEL_B               1
#       define R600_D1GRPH_GREEN_SEL_A               2
#       define R600_D1GRPH_GREEN_SEL_R               3
#       define R600_D1GRPH_BLUE_CROSSBAR(x)          (((x) & 0x3) << 8)
#       define R600_D1GRPH_BLUE_SEL_B                0
#       define R600_D1GRPH_BLUE_SEL_A                1
#       define R600_D1GRPH_BLUE_SEL_R                2
#       define R600_D1GRPH_BLUE_SEL_G                3
#       define R600_D1GRPH_ALPHA_CROSSBAR(x)         (((x) & 0x3) << 10)
#       define R600_D1GRPH_ALPHA_SEL_A               0
#       define R600_D1GRPH_ALPHA_SEL_R               1
#       define R600_D1GRPH_ALPHA_SEL_G               2
#       define R600_D1GRPH_ALPHA_SEL_B               3

#define R600_HDP_NONSURFACE_BASE                                0x2c04

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.