drivers/gpu/drm/radeon/radeon_combios.c

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/radeon/radeon_combios.c

Extension

.c

Size

104198 bytes

Lines

3609

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.
• Allocates kernel memory; connect allocation flags and lifetime to context constraints.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/pci.h
• drm/drm_device.h
• drm/drm_edid.h
• drm/radeon_drm.h
• radeon.h
• radeon_legacy_encoders.h
• atom.h
• asm/machdep.h
• asm/pmac_feature.h
• asm/prom.h

Detected Declarations

• enum radeon_combios_table_offset
• enum radeon_combios_ddc
• enum radeon_combios_connector
• function combios_get_table_offset
• function radeon_combios_check_hardcoded_edid
• function radeon_bios_get_hardcoded_edid
• function combios_setup_i2c_bus
• function radeon_combios_get_i2c_info_from_table
• function radeon_combios_i2c_init
• function radeon_combios_get_clock_info
• function radeon_combios_sideport_present
• function radeon_legacy_get_primary_dac_info_from_table
• function radeon_combios_get_tv_info
• function radeon_legacy_get_tv_dac_info_from_table
• function radeon_legacy_get_tmds_info_from_table
• function radeon_legacy_get_tmds_info_from_combios
• function radeon_legacy_get_ext_tmds_info_from_table
• function radeon_legacy_get_ext_tmds_info_from_combios
• function radeon_get_legacy_connector_info_from_table
• function of_machine_is_compatible
• function of_machine_is_compatible
• function of_machine_is_compatible
• function of_machine_is_compatible
• function of_machine_is_compatible
• function radeon_apply_legacy_quirks
• function radeon_apply_legacy_tv_quirks
• function combios_check_dl_dvi
• function radeon_get_legacy_connector_info_from_bios
• function radeon_combios_get_power_modes
• function radeon_external_tmds_setup
• function radeon_combios_external_tmds_setup
• function combios_parse_mmio_table
• function combios_parse_pll_table
• function combios_parse_ram_reset_table
• function combios_detect_ram
• function combios_write_ram_size
• function radeon_combios_asic_init
• function radeon_combios_initialize_bios_scratch_regs
• function radeon_combios_output_lock
• function radeon_combios_connected_scratch_regs
• function radeon_combios_encoder_crtc_scratch_regs
• function radeon_combios_encoder_dpms_scratch_regs

Annotated Snippet

if (check_offset) {
			rev = RBIOS8(check_offset);
			if (rev > 0) {
				check_offset = RBIOS16(check_offset + 0x3);
				if (check_offset)
					offset = check_offset;
			}
		}
		break;
	case COMBIOS_ASIC_INIT_4_TABLE:	/* offset from misc info */
		check_offset =
		    combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		if (check_offset) {
			rev = RBIOS8(check_offset);
			if (rev > 0) {
				check_offset = RBIOS16(check_offset + 0x5);
				if (check_offset)
					offset = check_offset;
			}
		}
		break;
	case COMBIOS_DETECTED_MEM_TABLE:	/* offset from misc info */
		check_offset =
		    combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		if (check_offset) {
			rev = RBIOS8(check_offset);
			if (rev > 0) {
				check_offset = RBIOS16(check_offset + 0x7);
				if (check_offset)
					offset = check_offset;
			}
		}
		break;
	case COMBIOS_ASIC_INIT_5_TABLE:	/* offset from misc info */
		check_offset =
		    combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		if (check_offset) {
			rev = RBIOS8(check_offset);
			if (rev == 2) {
				check_offset = RBIOS16(check_offset + 0x9);
				if (check_offset)
					offset = check_offset;
			}
		}
		break;
	case COMBIOS_RAM_RESET_TABLE:	/* offset from mem config */
		check_offset =
		    combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
		if (check_offset) {
			while (RBIOS8(check_offset++));
			check_offset += 2;
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_POWERPLAY_INFO_TABLE:	/* offset from mobile info */
		check_offset =
		    combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		if (check_offset) {
			check_offset = RBIOS16(check_offset + 0x11);
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_GPIO_INFO_TABLE:	/* offset from mobile info */
		check_offset =
		    combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		if (check_offset) {
			check_offset = RBIOS16(check_offset + 0x13);
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_LCD_DDC_INFO_TABLE:	/* offset from mobile info */
		check_offset =
		    combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		if (check_offset) {
			check_offset = RBIOS16(check_offset + 0x15);
			if (check_offset)
				offset = check_offset;
		}
		break;
	case COMBIOS_TMDS_POWER_TABLE:	/* offset from mobile info */
		check_offset =
		    combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		if (check_offset) {
			check_offset = RBIOS16(check_offset + 0x17);
			if (check_offset)
				offset = check_offset;
		}

Annotation

• Immediate include surface: `linux/pci.h`, `drm/drm_device.h`, `drm/drm_edid.h`, `drm/radeon_drm.h`, `radeon.h`, `radeon_legacy_encoders.h`, `atom.h`, `asm/machdep.h`.
• Detected declarations: `enum radeon_combios_table_offset`, `enum radeon_combios_ddc`, `enum radeon_combios_connector`, `function combios_get_table_offset`, `function radeon_combios_check_hardcoded_edid`, `function radeon_bios_get_hardcoded_edid`, `function combios_setup_i2c_bus`, `function radeon_combios_get_i2c_info_from_table`, `function radeon_combios_i2c_init`, `function radeon_combios_get_clock_info`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.