drivers/gpu/drm/radeon/radeon_legacy_tv.c

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/radeon/radeon_legacy_tv.c

Extension

.c

Size

27175 bytes

Lines

912

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• drm/drm_device.h
• radeon.h

Detected Declarations

• struct radeon_tv_mode_constants
• function radeon_wait_pll_lock
• function radeon_legacy_tv_write_fifo
• function radeon_legacy_tv_read_fifo
• function radeon_get_htiming_tables_addr
• function radeon_get_vtiming_tables_addr
• function radeon_restore_tv_timing_tables
• function radeon_legacy_write_tv_restarts
• function radeon_legacy_tv_init_restarts
• function radeon_legacy_tv_mode_set
• function radeon_legacy_tv_adjust_crtc_reg
• function get_post_div
• function radeon_legacy_tv_adjust_pll1
• function radeon_legacy_tv_adjust_pll2

Annotated Snippet

struct radeon_tv_mode_constants {
	uint16_t hor_resolution;
	uint16_t ver_resolution;
	enum radeon_tv_std standard;
	uint16_t hor_total;
	uint16_t ver_total;
	uint16_t hor_start;
	uint16_t hor_syncstart;
	uint16_t ver_syncstart;
	unsigned def_restart;
	uint16_t crtcPLL_N;
	uint8_t  crtcPLL_M;
	uint8_t  crtcPLL_post_div;
	unsigned pix_to_tv;
};

static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = {
	0x0007,
	0x003f,
	0x0263,
	0x0a24,
	0x2a6b,
	0x0a36,
	0x126d, /* H_TABLE_POS1 */
	0x1bfe,
	0x1a8f, /* H_TABLE_POS2 */
	0x1ec7,
	0x3863,
	0x1bfe,
	0x1bfe,
	0x1a2a,
	0x1e95,
	0x0e31,
	0x201b,
	0
};

static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = {
	0x2001,
	0x200d,
	0x1006,
	0x0c06,
	0x1006,
	0x1818,
	0x21e3,
	0x1006,
	0x0c06,
	0x1006,
	0x1817,
	0x21d4,
	0x0002,
	0
};

static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = {
	0x0007,
	0x0058,
	0x027c,
	0x0a31,
	0x2a77,
	0x0a95,
	0x124f, /* H_TABLE_POS1 */
	0x1bfe,
	0x1b22, /* H_TABLE_POS2 */
	0x1ef9,
	0x387c,
	0x1bfe,
	0x1bfe,
	0x1b31,
	0x1eb5,
	0x0e43,
	0x201b,
	0
};

static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = {
	0x2001,
	0x200c,
	0x1005,
	0x0c05,
	0x1005,
	0x1401,
	0x1821,
	0x2240,
	0x1005,
	0x0c05,
	0x1005,
	0x1401,
	0x1822,
	0x2230,

Annotation

• Immediate include surface: `drm/drm_device.h`, `radeon.h`.
• Detected declarations: `struct radeon_tv_mode_constants`, `function radeon_wait_pll_lock`, `function radeon_legacy_tv_write_fifo`, `function radeon_legacy_tv_read_fifo`, `function radeon_get_htiming_tables_addr`, `function radeon_get_vtiming_tables_addr`, `function radeon_restore_tv_timing_tables`, `function radeon_legacy_write_tv_restarts`, `function radeon_legacy_tv_init_restarts`, `function radeon_legacy_tv_mode_set`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.