drivers/gpu/drm/radeon/rs780d.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/radeon/rs780d.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/radeon/rs780d.h
Extension
.h
Size
7453 bytes
Lines
172
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __RS780D_H__
#define __RS780D_H__

#define CG_SPLL_FUNC_CNTL                                 0x600
#       define SPLL_RESET                                (1 << 0)
#       define SPLL_SLEEP                                (1 << 1)
#       define SPLL_REF_DIV(x)                           ((x) << 2)
#       define SPLL_REF_DIV_MASK                         (7 << 2)
#       define SPLL_REF_DIV_SHIFT                        2
#       define SPLL_FB_DIV(x)                            ((x) << 5)
#       define SPLL_FB_DIV_MASK                          (0xff << 2)
#       define SPLL_FB_DIV_SHIFT                         2
#       define SPLL_PULSEEN                              (1 << 13)
#       define SPLL_PULSENUM(x)                          ((x) << 14)
#       define SPLL_PULSENUM_MASK                        (3 << 14)
#       define SPLL_SW_HILEN(x)                          ((x) << 16)
#       define SPLL_SW_HILEN_MASK                        (0xf << 16)
#       define SPLL_SW_HILEN_SHIFT                       16
#       define SPLL_SW_LOLEN(x)                          ((x) << 20)
#       define SPLL_SW_LOLEN_MASK                        (0xf << 20)
#       define SPLL_SW_LOLEN_SHIFT                       20
#       define SPLL_DIVEN                                (1 << 24)
#       define SPLL_BYPASS_EN                            (1 << 25)
#       define SPLL_CHG_STATUS                           (1 << 29)
#       define SPLL_CTLREQ                               (1 << 30)
#       define SPLL_CTLACK                               (1 << 31)

/* RS780/RS880 PM */
#define	FVTHROT_CNTRL_REG				0x3000
#define		DONT_WAIT_FOR_FBDIV_WRAP		(1 << 0)
#define		MINIMUM_CIP(x)				((x) << 1)
#define		MINIMUM_CIP_SHIFT			1
#define		MINIMUM_CIP_MASK			0x1fffffe
#define		REFRESH_RATE_DIVISOR(x)			((x) << 25)
#define		REFRESH_RATE_DIVISOR_SHIFT		25
#define		REFRESH_RATE_DIVISOR_MASK		(0x3 << 25)
#define		ENABLE_FV_THROT				(1 << 27)
#define		ENABLE_FV_UPDATE			(1 << 28)
#define		TREND_SEL_MODE				(1 << 29)
#define		FORCE_TREND_SEL				(1 << 30)
#define		ENABLE_FV_THROT_IO			(1 << 31)
#define	FVTHROT_TARGET_REG				0x3004
#define		TARGET_IDLE_COUNT(x)			((x) << 0)
#define		TARGET_IDLE_COUNT_MASK			0xffffff
#define		TARGET_IDLE_COUNT_SHIFT			0
#define	FVTHROT_CB1					0x3008
#define	FVTHROT_CB2					0x300c
#define	FVTHROT_CB3					0x3010
#define	FVTHROT_CB4					0x3014
#define	FVTHROT_UTC0					0x3018
#define	FVTHROT_UTC1					0x301c
#define	FVTHROT_UTC2					0x3020
#define	FVTHROT_UTC3					0x3024
#define	FVTHROT_UTC4					0x3028
#define	FVTHROT_DTC0					0x302c
#define	FVTHROT_DTC1					0x3030
#define	FVTHROT_DTC2					0x3034
#define	FVTHROT_DTC3					0x3038
#define	FVTHROT_DTC4					0x303c
#define	FVTHROT_FBDIV_REG0				0x3040
#define		MIN_FEEDBACK_DIV(x)			((x) << 0)
#define		MIN_FEEDBACK_DIV_MASK			0xfff
#define		MIN_FEEDBACK_DIV_SHIFT			0
#define		MAX_FEEDBACK_DIV(x)			((x) << 12)
#define		MAX_FEEDBACK_DIV_MASK			(0xfff << 12)
#define		MAX_FEEDBACK_DIV_SHIFT			12
#define	FVTHROT_FBDIV_REG1				0x3044
#define		MAX_FEEDBACK_STEP(x)			((x) << 0)
#define		MAX_FEEDBACK_STEP_MASK			0xfff
#define		MAX_FEEDBACK_STEP_SHIFT			0
#define		STARTING_FEEDBACK_DIV(x)		((x) << 12)
#define		STARTING_FEEDBACK_DIV_MASK		(0xfff << 12)
#define		STARTING_FEEDBACK_DIV_SHIFT		12
#define		FORCE_FEEDBACK_DIV			(1 << 24)
#define	FVTHROT_FBDIV_REG2				0x3048
#define		FORCED_FEEDBACK_DIV(x)			((x) << 0)
#define		FORCED_FEEDBACK_DIV_MASK		0xfff
#define		FORCED_FEEDBACK_DIV_SHIFT		0
#define		FB_DIV_TIMER_VAL(x)			((x) << 12)
#define		FB_DIV_TIMER_VAL_MASK			(0xffff << 12)
#define		FB_DIV_TIMER_VAL_SHIFT			12
#define	FVTHROT_FB_US_REG0				0x304c
#define	FVTHROT_FB_US_REG1				0x3050
#define	FVTHROT_FB_DS_REG0				0x3054
#define	FVTHROT_FB_DS_REG1				0x3058
#define	FVTHROT_PWM_CTRL_REG0				0x305c
#define		STARTING_PWM_HIGHTIME(x)		((x) << 0)
#define		STARTING_PWM_HIGHTIME_MASK		0xfff
#define		STARTING_PWM_HIGHTIME_SHIFT		0
#define		NUMBER_OF_CYCLES_IN_PERIOD(x)		((x) << 12)

Annotation

Implementation Notes