drivers/gpu/drm/radeon/rv515.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/radeon/rv515.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/radeon/rv515.c- Extension
.c- Size
- 39934 bytes
- Lines
- 1277
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/debugfs.hlinux/seq_file.hlinux/slab.hdrm/drm_device.hdrm/drm_file.hatom.hradeon.hradeon_asic.hrv515_reg_safe.hrv515d.h
Detected Declarations
struct rv515_watermarkfunction rv515_ring_startfunction rv515_mc_wait_for_idlefunction rv515_vga_render_disablefunction rv515_gpu_initfunction rv515_vram_get_typefunction rv515_mc_initfunction rv515_mc_rregfunction rv515_mc_wregfunction rv515_debugfs_pipes_info_showfunction rv515_debugfs_ga_info_showfunction rv515_debugfsfunction rv515_mc_stopfunction rv515_mc_resumefunction rv515_mc_programfunction rv515_clock_startupfunction rv515_startupfunction rv515_resumefunction rv515_suspendfunction rv515_set_safe_registersfunction rv515_finifunction rv515_initfunction atom_rv515_force_tv_scalerfunction rv515_crtc_bandwidth_computefunction rv515_compute_mode_priorityfunction rv515_bandwidth_avivo_updatefunction rv515_bandwidth_update
Annotated Snippet
struct rv515_watermark {
u32 lb_request_fifo_depth;
fixed20_12 num_line_pair;
fixed20_12 estimated_width;
fixed20_12 worst_case_latency;
fixed20_12 consumption_rate;
fixed20_12 active_time;
fixed20_12 dbpp;
fixed20_12 priority_mark_max;
fixed20_12 priority_mark;
fixed20_12 sclk;
};
static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
struct radeon_crtc *crtc,
struct rv515_watermark *wm,
bool low)
{
struct drm_display_mode *mode = &crtc->base.mode;
fixed20_12 a, b, c;
fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
fixed20_12 sclk;
u32 selected_sclk;
if (!crtc->base.enabled) {
/* FIXME: wouldn't it better to set priority mark to maximum */
wm->lb_request_fifo_depth = 4;
return;
}
/* rv6xx, rv7xx */
if ((rdev->family >= CHIP_RV610) &&
(rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
selected_sclk = radeon_dpm_get_sclk(rdev, low);
else
selected_sclk = rdev->pm.current_sclk;
/* sclk in Mhz */
a.full = dfixed_const(100);
sclk.full = dfixed_const(selected_sclk);
sclk.full = dfixed_div(sclk, a);
if (crtc->vsc.full > dfixed_const(2))
wm->num_line_pair.full = dfixed_const(2);
else
wm->num_line_pair.full = dfixed_const(1);
b.full = dfixed_const(mode->crtc_hdisplay);
c.full = dfixed_const(256);
a.full = dfixed_div(b, c);
request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
if (a.full < dfixed_const(4)) {
wm->lb_request_fifo_depth = 4;
} else {
wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
}
/* Determine consumption rate
* pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
* vtaps = number of vertical taps,
* vsc = vertical scaling ratio, defined as source/destination
* hsc = horizontal scaling ration, defined as source/destination
*/
a.full = dfixed_const(mode->clock);
b.full = dfixed_const(1000);
a.full = dfixed_div(a, b);
pclk.full = dfixed_div(b, a);
if (crtc->rmx_type != RMX_OFF) {
b.full = dfixed_const(2);
if (crtc->vsc.full > b.full)
b.full = crtc->vsc.full;
b.full = dfixed_mul(b, crtc->hsc);
c.full = dfixed_const(2);
b.full = dfixed_div(b, c);
consumption_time.full = dfixed_div(pclk, b);
} else {
consumption_time.full = pclk.full;
}
a.full = dfixed_const(1);
wm->consumption_rate.full = dfixed_div(a, consumption_time);
/* Determine line time
* LineTime = total time for one line of displayhtotal
* LineTime = total number of horizontal pixels
* pclk = pixel clock period(ns)
*/
a.full = dfixed_const(crtc->base.mode.crtc_htotal);
Annotation
- Immediate include surface: `linux/debugfs.h`, `linux/seq_file.h`, `linux/slab.h`, `drm/drm_device.h`, `drm/drm_file.h`, `atom.h`, `radeon.h`, `radeon_asic.h`.
- Detected declarations: `struct rv515_watermark`, `function rv515_ring_start`, `function rv515_mc_wait_for_idle`, `function rv515_vga_render_disable`, `function rv515_gpu_init`, `function rv515_vram_get_type`, `function rv515_mc_init`, `function rv515_mc_rreg`, `function rv515_mc_wreg`, `function rv515_debugfs_pipes_info_show`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.