drivers/gpu/drm/radeon/rv730d.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/radeon/rv730d.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/radeon/rv730d.h
Extension: .h
Size: 7475 bytes
Lines: 166
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef RV730_H
#define RV730_H

#define	CG_SPLL_FUNC_CNTL				0x600
#define		SPLL_RESET				(1 << 0)
#define		SPLL_SLEEP				(1 << 1)
#define		SPLL_DIVEN				(1 << 2)
#define		SPLL_BYPASS_EN				(1 << 3)
#define		SPLL_REF_DIV(x)				((x) << 4)
#define		SPLL_REF_DIV_MASK			(0x3f << 4)
#define		SPLL_HILEN(x)				((x) << 12)
#define		SPLL_HILEN_MASK				(0xf << 12)
#define		SPLL_LOLEN(x)				((x) << 16)
#define		SPLL_LOLEN_MASK				(0xf << 16)
#define	CG_SPLL_FUNC_CNTL_2				0x604
#define		SCLK_MUX_SEL(x)				((x) << 0)
#define		SCLK_MUX_SEL_MASK			(0x1ff << 0)
#define	CG_SPLL_FUNC_CNTL_3				0x608
#define		SPLL_FB_DIV(x)				((x) << 0)
#define		SPLL_FB_DIV_MASK			(0x3ffffff << 0)
#define		SPLL_DITHEN				(1 << 28)

#define	CG_MPLL_FUNC_CNTL				0x624
#define		MPLL_RESET				(1 << 0)
#define		MPLL_SLEEP				(1 << 1)
#define		MPLL_DIVEN				(1 << 2)
#define		MPLL_BYPASS_EN				(1 << 3)
#define		MPLL_REF_DIV(x)				((x) << 4)
#define		MPLL_REF_DIV_MASK			(0x3f << 4)
#define		MPLL_HILEN(x)				((x) << 12)
#define		MPLL_HILEN_MASK				(0xf << 12)
#define		MPLL_LOLEN(x)				((x) << 16)
#define		MPLL_LOLEN_MASK				(0xf << 16)
#define	CG_MPLL_FUNC_CNTL_2				0x628
#define		MCLK_MUX_SEL(x)				((x) << 0)
#define		MCLK_MUX_SEL_MASK			(0x1ff << 0)
#define	CG_MPLL_FUNC_CNTL_3				0x62c
#define		MPLL_FB_DIV(x)				((x) << 0)
#define		MPLL_FB_DIV_MASK			(0x3ffffff << 0)
#define		MPLL_DITHEN				(1 << 28)

#define	CG_TCI_MPLL_SPREAD_SPECTRUM			0x634
#define	CG_TCI_MPLL_SPREAD_SPECTRUM_2			0x638
#define GENERAL_PWRMGT                                  0x63c
#       define GLOBAL_PWRMGT_EN                         (1 << 0)
#       define STATIC_PM_EN                             (1 << 1)
#       define THERMAL_PROTECTION_DIS                   (1 << 2)
#       define THERMAL_PROTECTION_TYPE                  (1 << 3)
#       define ENABLE_GEN2PCIE                          (1 << 4)
#       define ENABLE_GEN2XSP                           (1 << 5)
#       define SW_SMIO_INDEX(x)                         ((x) << 6)
#       define SW_SMIO_INDEX_MASK                       (3 << 6)
#       define LOW_VOLT_D2_ACPI                         (1 << 8)
#       define LOW_VOLT_D3_ACPI                         (1 << 9)
#       define VOLT_PWRMGT_EN                           (1 << 10)
#       define BACKBIAS_PAD_EN                          (1 << 18)
#       define BACKBIAS_VALUE                           (1 << 19)
#       define DYN_SPREAD_SPECTRUM_EN                   (1 << 23)
#       define AC_DC_SW                                 (1 << 24)

#define SCLK_PWRMGT_CNTL                                  0x644
#       define SCLK_PWRMGT_OFF                            (1 << 0)
#       define SCLK_LOW_D1                                (1 << 1)
#       define FIR_RESET                                  (1 << 4)
#       define FIR_FORCE_TREND_SEL                        (1 << 5)
#       define FIR_TREND_MODE                             (1 << 6)
#       define DYN_GFX_CLK_OFF_EN                         (1 << 7)
#       define GFX_CLK_FORCE_ON                           (1 << 8)
#       define GFX_CLK_REQUEST_OFF                        (1 << 9)
#       define GFX_CLK_FORCE_OFF                          (1 << 10)
#       define GFX_CLK_OFF_ACPI_D1                        (1 << 11)
#       define GFX_CLK_OFF_ACPI_D2                        (1 << 12)
#       define GFX_CLK_OFF_ACPI_D3                        (1 << 13)

#define	TCI_MCLK_PWRMGT_CNTL				0x648
#       define MPLL_PWRMGT_OFF                          (1 << 5)
#       define DLL_READY                                (1 << 6)
#       define MC_INT_CNTL                              (1 << 7)
#       define MRDCKA_SLEEP                             (1 << 8)
#       define MRDCKB_SLEEP                             (1 << 9)
#       define MRDCKC_SLEEP                             (1 << 10)
#       define MRDCKD_SLEEP                             (1 << 11)
#       define MRDCKE_SLEEP                             (1 << 12)
#       define MRDCKF_SLEEP                             (1 << 13)
#       define MRDCKG_SLEEP                             (1 << 14)
#       define MRDCKH_SLEEP                             (1 << 15)
#       define MRDCKA_RESET                             (1 << 16)
#       define MRDCKB_RESET                             (1 << 17)
#       define MRDCKC_RESET                             (1 << 18)
#       define MRDCKD_RESET                             (1 << 19)

Annotation

Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.