drivers/gpu/drm/radeon/rv740_dpm.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/radeon/rv740_dpm.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/radeon/rv740_dpm.c
Extension
.c
Size
12700 bytes
Lines
419
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dll_speed_setting {
	u16 min;
	u16 max;
	u32 dll_speed;
};

static struct dll_speed_setting dll_speed_table[16] =
{
	{ 270, 320, 0x0f },
	{ 240, 270, 0x0e },
	{ 200, 240, 0x0d },
	{ 180, 200, 0x0c },
	{ 160, 180, 0x0b },
	{ 140, 160, 0x0a },
	{ 120, 140, 0x09 },
	{ 110, 120, 0x08 },
	{  95, 110, 0x07 },
	{  85,  95, 0x06 },
	{  78,  85, 0x05 },
	{  70,  78, 0x04 },
	{  65,  70, 0x03 },
	{  60,  65, 0x02 },
	{  42,  60, 0x01 },
	{  00,  42, 0x00 }
};

u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock)
{
	int i;
	u32 factor;
	u16 data_rate;

	if (is_gddr5)
		factor = 4;
	else
		factor = 2;

	data_rate = (u16)(memory_clock * factor / 1000);

	if (data_rate < dll_speed_table[0].max) {
		for (i = 0; i < 16; i++) {
			if (data_rate > dll_speed_table[i].min &&
			    data_rate <= dll_speed_table[i].max)
				return dll_speed_table[i].dll_speed;
		}
	}

	DRM_DEBUG_KMS("Target MCLK greater than largest MCLK in DLL speed table\n");

	return 0x0f;
}

int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
			      RV770_SMC_SCLK_VALUE *sclk)
{
	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
	struct atom_clock_dividers dividers;
	u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;
	u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;
	u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;
	u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum;
	u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2;
	u64 tmp;
	u32 reference_clock = rdev->clock.spll.reference_freq;
	u32 reference_divider;
	u32 fbdiv;
	int ret;

	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
					     engine_clock, false, &dividers);
	if (ret)
		return ret;

	reference_divider = 1 + dividers.ref_div;

	tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
	do_div(tmp, reference_clock);
	fbdiv = (u32) tmp;

	spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
	spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);

	spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
	spll_func_cntl_2 |= SCLK_MUX_SEL(2);

	spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
	spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
	spll_func_cntl_3 |= SPLL_DITHEN;

Annotation

Implementation Notes