drivers/gpu/drm/radeon/rv770_dpm.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/radeon/rv770_dpm.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/radeon/rv770_dpm.h- Extension
.h- Size
- 9664 bytes
- Lines
- 286
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
radeon.hrv770_smc.h
Detected Declarations
struct rv770_clock_registersstruct rv730_clock_registersstruct vddc_table_entrystruct rv7xx_power_infostruct rv7xx_plstruct rv7xx_ps
Annotated Snippet
struct rv770_clock_registers {
u32 cg_spll_func_cntl;
u32 cg_spll_func_cntl_2;
u32 cg_spll_func_cntl_3;
u32 cg_spll_spread_spectrum;
u32 cg_spll_spread_spectrum_2;
u32 mpll_ad_func_cntl;
u32 mpll_ad_func_cntl_2;
u32 mpll_dq_func_cntl;
u32 mpll_dq_func_cntl_2;
u32 mclk_pwrmgt_cntl;
u32 dll_cntl;
u32 mpll_ss1;
u32 mpll_ss2;
};
struct rv730_clock_registers {
u32 cg_spll_func_cntl;
u32 cg_spll_func_cntl_2;
u32 cg_spll_func_cntl_3;
u32 cg_spll_spread_spectrum;
u32 cg_spll_spread_spectrum_2;
u32 mclk_pwrmgt_cntl;
u32 dll_cntl;
u32 mpll_func_cntl;
u32 mpll_func_cntl2;
u32 mpll_func_cntl3;
u32 mpll_ss;
u32 mpll_ss2;
};
union r7xx_clock_registers {
struct rv770_clock_registers rv770;
struct rv730_clock_registers rv730;
};
struct vddc_table_entry {
u16 vddc;
u8 vddc_index;
u8 high_smio;
u32 low_smio;
};
#define MAX_NO_OF_MVDD_VALUES 2
#define MAX_NO_VREG_STEPS 32
struct rv7xx_power_info {
/* flags */
bool mem_gddr5;
bool pcie_gen2;
bool dynamic_pcie_gen2;
bool acpi_pcie_gen2;
bool boot_in_gen2;
bool voltage_control; /* vddc */
bool mvdd_control;
bool sclk_ss;
bool mclk_ss;
bool dynamic_ss;
bool gfx_clock_gating;
bool mg_clock_gating;
bool mgcgtssm;
bool power_gating;
bool thermal_protection;
bool display_gap;
bool dcodt;
bool ulps;
/* registers */
union r7xx_clock_registers clk_regs;
u32 s0_vid_lower_smio_cntl;
/* voltage */
u32 vddc_mask_low;
u32 mvdd_mask_low;
u32 mvdd_split_frequency;
u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];
u16 max_vddc;
u16 max_vddc_in_table;
u16 min_vddc_in_table;
struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS];
u8 valid_vddc_entries;
/* dc odt */
u32 mclk_odt_threshold;
u8 odt_value_0[2];
u8 odt_value_1[2];
/* stored values */
u32 boot_sclk;
u16 acpi_vddc;
u32 ref_div;
u32 active_auto_throttle_sources;
u32 mclk_stutter_mode_threshold;
u32 mclk_strobe_mode_threshold;
Annotation
- Immediate include surface: `radeon.h`, `rv770_smc.h`.
- Detected declarations: `struct rv770_clock_registers`, `struct rv730_clock_registers`, `struct vddc_table_entry`, `struct rv7xx_power_info`, `struct rv7xx_pl`, `struct rv7xx_ps`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.