drivers/gpu/drm/radeon/rv770d.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/radeon/rv770d.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/radeon/rv770d.h
Extension
.h
Size
46120 bytes
Lines
1016
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef RV770_H
#define RV770_H

#define R7XX_MAX_SH_GPRS           256
#define R7XX_MAX_TEMP_GPRS         16
#define R7XX_MAX_SH_THREADS        256
#define R7XX_MAX_SH_STACK_ENTRIES  4096
#define R7XX_MAX_BACKENDS          8
#define R7XX_MAX_BACKENDS_MASK     0xff
#define R7XX_MAX_SIMDS             16
#define R7XX_MAX_SIMDS_MASK        0xffff
#define R7XX_MAX_PIPES             8
#define R7XX_MAX_PIPES_MASK        0xff

/* discrete uvd clocks */
#define CG_UPLL_FUNC_CNTL				0x718
#	define UPLL_RESET_MASK				0x00000001
#	define UPLL_SLEEP_MASK				0x00000002
#	define UPLL_BYPASS_EN_MASK			0x00000004
#	define UPLL_CTLREQ_MASK				0x00000008
#	define UPLL_REF_DIV(x)				((x) << 16)
#	define UPLL_REF_DIV_MASK			0x003F0000
#	define UPLL_CTLACK_MASK				0x40000000
#	define UPLL_CTLACK2_MASK			0x80000000
#define CG_UPLL_FUNC_CNTL_2				0x71c
#	define UPLL_SW_HILEN(x)				((x) << 0)
#	define UPLL_SW_LOLEN(x)				((x) << 4)
#	define UPLL_SW_HILEN2(x)			((x) << 8)
#	define UPLL_SW_LOLEN2(x)			((x) << 12)
#	define UPLL_SW_MASK				0x0000FFFF
#	define VCLK_SRC_SEL(x)				((x) << 20)
#	define VCLK_SRC_SEL_MASK			0x01F00000
#	define DCLK_SRC_SEL(x)				((x) << 25)
#	define DCLK_SRC_SEL_MASK			0x3E000000
#define CG_UPLL_FUNC_CNTL_3				0x720
#	define UPLL_FB_DIV(x)				((x) << 0)
#	define UPLL_FB_DIV_MASK				0x01FFFFFF

/* pm registers */
#define	SMC_SRAM_ADDR					0x200
#define		SMC_SRAM_AUTO_INC_DIS				(1 << 16)
#define	SMC_SRAM_DATA					0x204
#define	SMC_IO						0x208
#define		SMC_RST_N					(1 << 0)
#define		SMC_STOP_MODE					(1 << 2)
#define		SMC_CLK_EN					(1 << 11)
#define	SMC_MSG						0x20c
#define		HOST_SMC_MSG(x)					((x) << 0)
#define		HOST_SMC_MSG_MASK				(0xff << 0)
#define		HOST_SMC_MSG_SHIFT				0
#define		HOST_SMC_RESP(x)				((x) << 8)
#define		HOST_SMC_RESP_MASK				(0xff << 8)
#define		HOST_SMC_RESP_SHIFT				8
#define		SMC_HOST_MSG(x)					((x) << 16)
#define		SMC_HOST_MSG_MASK				(0xff << 16)
#define		SMC_HOST_MSG_SHIFT				16
#define		SMC_HOST_RESP(x)				((x) << 24)
#define		SMC_HOST_RESP_MASK				(0xff << 24)
#define		SMC_HOST_RESP_SHIFT				24

#define	SMC_ISR_FFD8_FFDB				0x218

#define	CG_SPLL_FUNC_CNTL				0x600
#define		SPLL_RESET				(1 << 0)
#define		SPLL_SLEEP				(1 << 1)
#define		SPLL_DIVEN				(1 << 2)
#define		SPLL_BYPASS_EN				(1 << 3)
#define		SPLL_REF_DIV(x)				((x) << 4)
#define		SPLL_REF_DIV_MASK			(0x3f << 4)
#define		SPLL_HILEN(x)				((x) << 12)
#define		SPLL_HILEN_MASK				(0xf << 12)
#define		SPLL_LOLEN(x)				((x) << 16)
#define		SPLL_LOLEN_MASK				(0xf << 16)
#define	CG_SPLL_FUNC_CNTL_2				0x604
#define		SCLK_MUX_SEL(x)				((x) << 0)
#define		SCLK_MUX_SEL_MASK			(0x1ff << 0)
#define		SCLK_MUX_UPDATE				(1 << 26)
#define	CG_SPLL_FUNC_CNTL_3				0x608
#define		SPLL_FB_DIV(x)				((x) << 0)
#define		SPLL_FB_DIV_MASK			(0x3ffffff << 0)
#define		SPLL_DITHEN				(1 << 28)
#define	CG_SPLL_STATUS					0x60c
#define		SPLL_CHG_STATUS				(1 << 1)

#define	SPLL_CNTL_MODE					0x610
#define		SPLL_DIV_SYNC				(1 << 5)

#define MPLL_CNTL_MODE                                  0x61c
#       define MPLL_MCLK_SEL                            (1 << 11)
#       define RV730_MPLL_MCLK_SEL                      (1 << 25)

Annotation

Implementation Notes