drivers/gpu/drm/radeon/sumo_dpm.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/radeon/sumo_dpm.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/radeon/sumo_dpm.c- Extension
.c- Size
- 55925 bytes
- Lines
- 1967
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
radeon.hradeon_asic.hsumod.hr600_dpm.hcypress_dpm.hsumo_dpm.hlinux/seq_file.h
Detected Declarations
function sumo_gfx_clockgating_enablefunction sumo_mg_clockgating_enablefunction sumo_program_gitfunction sumo_program_grsdfunction sumo_gfx_clockgating_initializefunction sumo_gfx_powergating_initializefunction sumo_gfx_powergating_enablefunction sumo_enable_clock_power_gatingfunction sumo_disable_clock_power_gatingfunction sumo_calculate_bspfunction sumo_init_bspfunction sumo_program_bspfunction sumo_write_atfunction sumo_program_atfunction sumo_program_tpfunction sumo_program_vcfunction sumo_clear_vcfunction sumo_program_sstpfunction sumo_set_divider_valuefunction sumo_set_ds_dividersfunction sumo_set_ss_dividersfunction sumo_set_vidfunction sumo_set_allos_gnb_slowfunction sumo_program_power_levelfunction sumo_power_level_enablefunction sumo_dpm_enabledfunction sumo_start_dpmfunction sumo_stop_dpmfunction sumo_set_forced_modefunction sumo_set_forced_mode_enabledfunction sumo_wait_for_level_0function sumo_set_forced_mode_disabledfunction sumo_enable_power_level_0function sumo_patch_boost_statefunction sumo_pre_notify_alt_vddnb_changefunction sumo_post_notify_alt_vddnb_changefunction sumo_enable_boostfunction sumo_set_forced_levelfunction sumo_set_forced_level_0function sumo_program_wlfunction sumo_program_power_levels_0_to_nfunction sumo_enable_acpi_pmfunction sumo_program_power_level_enter_statefunction sumo_program_acpi_power_levelfunction sumo_program_bootup_statefunction sumo_setup_uvd_clocksfunction sumo_set_uvd_clock_before_set_eng_clockfunction sumo_set_uvd_clock_after_set_eng_clock
Annotated Snippet
if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {
if (ps->levels[i].ss_divider_index > 1)
ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;
}
if (ps->levels[i].ss_divider_index == 0)
ps->levels[i].ds_divider_index = 0;
if (ps->levels[i].ds_divider_index == 0)
ps->levels[i].ss_divider_index = 0;
if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
ps->levels[i].allow_gnb_slow = 1;
else if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) ||
(new_rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC))
ps->levels[i].allow_gnb_slow = 0;
else if (i == ps->num_levels - 1)
ps->levels[i].allow_gnb_slow = 0;
else
ps->levels[i].allow_gnb_slow = 1;
}
}
static void sumo_cleanup_asic(struct radeon_device *rdev)
{
sumo_take_smu_control(rdev, false);
}
static int sumo_set_thermal_temperature_range(struct radeon_device *rdev,
int min_temp, int max_temp)
{
int low_temp = 0 * 1000;
int high_temp = 255 * 1000;
if (low_temp < min_temp)
low_temp = min_temp;
if (high_temp > max_temp)
high_temp = max_temp;
if (high_temp < low_temp) {
DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
return -EINVAL;
}
WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
rdev->pm.dpm.thermal.min_temp = low_temp;
rdev->pm.dpm.thermal.max_temp = high_temp;
return 0;
}
static void sumo_update_current_ps(struct radeon_device *rdev,
struct radeon_ps *rps)
{
struct sumo_ps *new_ps = sumo_get_ps(rps);
struct sumo_power_info *pi = sumo_get_pi(rdev);
pi->current_rps = *rps;
pi->current_ps = *new_ps;
pi->current_rps.ps_priv = &pi->current_ps;
}
static void sumo_update_requested_ps(struct radeon_device *rdev,
struct radeon_ps *rps)
{
struct sumo_ps *new_ps = sumo_get_ps(rps);
struct sumo_power_info *pi = sumo_get_pi(rdev);
pi->requested_rps = *rps;
pi->requested_ps = *new_ps;
pi->requested_rps.ps_priv = &pi->requested_ps;
}
int sumo_dpm_enable(struct radeon_device *rdev)
{
struct sumo_power_info *pi = sumo_get_pi(rdev);
if (sumo_dpm_enabled(rdev))
return -EINVAL;
sumo_program_bootup_state(rdev);
sumo_init_bsp(rdev);
sumo_reset_am(rdev);
sumo_program_tp(rdev);
sumo_program_bootup_at(rdev);
sumo_start_am(rdev);
if (pi->enable_auto_thermal_throttling) {
sumo_program_ttp(rdev);
sumo_program_ttt(rdev);
Annotation
- Immediate include surface: `radeon.h`, `radeon_asic.h`, `sumod.h`, `r600_dpm.h`, `cypress_dpm.h`, `sumo_dpm.h`, `linux/seq_file.h`.
- Detected declarations: `function sumo_gfx_clockgating_enable`, `function sumo_mg_clockgating_enable`, `function sumo_program_git`, `function sumo_program_grsd`, `function sumo_gfx_clockgating_initialize`, `function sumo_gfx_powergating_initialize`, `function sumo_gfx_powergating_enable`, `function sumo_enable_clock_power_gating`, `function sumo_disable_clock_power_gating`, `function sumo_calculate_bsp`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.