drivers/gpu/drm/radeon/trinityd.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/radeon/trinityd.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/radeon/trinityd.h- Extension
.h- Size
- 11770 bytes
- Lines
- 229
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _TRINITYD_H_
#define _TRINITYD_H_
/* pm registers */
/* cg */
#define CG_CGTT_LOCAL_0 0x0
#define CG_CGTT_LOCAL_1 0x1
/* smc */
#define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000
# define STATE_VALID(x) ((x) << 0)
# define STATE_VALID_MASK (0xff << 0)
# define STATE_VALID_SHIFT 0
# define CLK_DIVIDER(x) ((x) << 8)
# define CLK_DIVIDER_MASK (0xff << 8)
# define CLK_DIVIDER_SHIFT 8
# define VID(x) ((x) << 16)
# define VID_MASK (0xff << 16)
# define VID_SHIFT 16
# define LVRT(x) ((x) << 24)
# define LVRT_MASK (0xff << 24)
# define LVRT_SHIFT 24
#define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004
# define DS_DIV(x) ((x) << 0)
# define DS_DIV_MASK (0xff << 0)
# define DS_DIV_SHIFT 0
# define DS_SH_DIV(x) ((x) << 8)
# define DS_SH_DIV_MASK (0xff << 8)
# define DS_SH_DIV_SHIFT 8
# define DISPLAY_WM(x) ((x) << 16)
# define DISPLAY_WM_MASK (0xff << 16)
# define DISPLAY_WM_SHIFT 16
# define VCE_WM(x) ((x) << 24)
# define VCE_WM_MASK (0xff << 24)
# define VCE_WM_SHIFT 24
#define SMU_SCLK_DPM_STATE_0_CNTL_3 0x1f00c
# define GNB_SLOW(x) ((x) << 0)
# define GNB_SLOW_MASK (0xff << 0)
# define GNB_SLOW_SHIFT 0
# define FORCE_NBPS1(x) ((x) << 8)
# define FORCE_NBPS1_MASK (0xff << 8)
# define FORCE_NBPS1_SHIFT 8
#define SMU_SCLK_DPM_STATE_0_AT 0x1f010
# define AT(x) ((x) << 0)
# define AT_MASK (0xff << 0)
# define AT_SHIFT 0
#define SMU_SCLK_DPM_STATE_0_PG_CNTL 0x1f014
# define PD_SCLK_DIVIDER(x) ((x) << 16)
# define PD_SCLK_DIVIDER_MASK (0xff << 16)
# define PD_SCLK_DIVIDER_SHIFT 16
#define SMU_SCLK_DPM_STATE_1_CNTL_0 0x1f020
#define SMU_SCLK_DPM_CNTL 0x1f100
# define SCLK_DPM_EN(x) ((x) << 0)
# define SCLK_DPM_EN_MASK (0xff << 0)
# define SCLK_DPM_EN_SHIFT 0
# define SCLK_DPM_BOOT_STATE(x) ((x) << 16)
# define SCLK_DPM_BOOT_STATE_MASK (0xff << 16)
# define SCLK_DPM_BOOT_STATE_SHIFT 16
# define VOLTAGE_CHG_EN(x) ((x) << 24)
# define VOLTAGE_CHG_EN_MASK (0xff << 24)
# define VOLTAGE_CHG_EN_SHIFT 24
#define SMU_SCLK_DPM_TT_CNTL 0x1f108
# define SCLK_TT_EN(x) ((x) << 0)
# define SCLK_TT_EN_MASK (0xff << 0)
# define SCLK_TT_EN_SHIFT 0
#define SMU_SCLK_DPM_TTT 0x1f10c
# define LT(x) ((x) << 0)
# define LT_MASK (0xffff << 0)
# define LT_SHIFT 0
# define HT(x) ((x) << 16)
# define HT_MASK (0xffff << 16)
# define HT_SHIFT 16
#define SMU_UVD_DPM_STATES 0x1f1a0
#define SMU_UVD_DPM_CNTL 0x1f1a4
#define SMU_S_PG_CNTL 0x1f118
# define DS_PG_EN(x) ((x) << 16)
# define DS_PG_EN_MASK (0xff << 16)
# define DS_PG_EN_SHIFT 16
#define GFX_POWER_GATING_CNTL 0x1f38c
# define PDS_DIV(x) ((x) << 0)
# define PDS_DIV_MASK (0xff << 0)Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.