drivers/gpu/drm/radeon/vce_v1_0.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/radeon/vce_v1_0.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/radeon/vce_v1_0.c
Extension
.c
Size
9074 bytes
Lines
385
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <linux/firmware.h>

#include "radeon.h"
#include "radeon_asic.h"
#include "sid.h"
#include "vce.h"

#define VCE_V1_0_FW_SIZE	(256 * 1024)
#define VCE_V1_0_STACK_SIZE	(64 * 1024)
#define VCE_V1_0_DATA_SIZE	(7808 * (RADEON_MAX_VCE_HANDLES + 1))

struct vce_v1_0_fw_signature
{
	int32_t off;
	uint32_t len;
	int32_t num;
	struct {
		uint32_t chip_id;
		uint32_t keyselect;
		uint32_t nonce[4];
		uint32_t sigval[4];
	} val[8];
};

/**
 * vce_v1_0_get_rptr - get read pointer
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring pointer
 *
 * Returns the current hardware read pointer
 */
uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
			   struct radeon_ring *ring)
{
	if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
		return RREG32(VCE_RB_RPTR);
	else
		return RREG32(VCE_RB_RPTR2);
}

/**
 * vce_v1_0_get_wptr - get write pointer
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring pointer
 *
 * Returns the current hardware write pointer
 */
uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
			   struct radeon_ring *ring)
{
	if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
		return RREG32(VCE_RB_WPTR);
	else
		return RREG32(VCE_RB_WPTR2);
}

/**
 * vce_v1_0_set_wptr - set write pointer
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring pointer
 *
 * Commits the write pointer to the hardware
 */
void vce_v1_0_set_wptr(struct radeon_device *rdev,
		       struct radeon_ring *ring)
{
	if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
		WREG32(VCE_RB_WPTR, ring->wptr);
	else
		WREG32(VCE_RB_WPTR2, ring->wptr);
}

void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable)
{
	u32 tmp;

	if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {
		tmp = RREG32(VCE_CLOCK_GATING_A);
		tmp |= CGC_DYN_CLOCK_MODE;
		WREG32(VCE_CLOCK_GATING_A, tmp);

		tmp = RREG32(VCE_UENC_CLOCK_GATING);
		tmp &= ~0x1ff000;
		tmp |= 0xff800000;
		WREG32(VCE_UENC_CLOCK_GATING, tmp);

		tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);

Annotation

Implementation Notes