drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
Extension
.c
Size
5207 bytes
Lines
218
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * RZ/G2L Display Unit DRM driver
 *
 * Copyright (C) 2023 Renesas Electronics Corporation
 *
 * Based on rcar_du_drv.c
 */

#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>

#include <drm/clients/drm_client_setup.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_drv.h>
#include <drm/drm_fbdev_dma.h>
#include <drm/drm_gem_dma_helper.h>
#include <drm/drm_print.h>
#include <drm/drm_probe_helper.h>

#include "rzg2l_du_drv.h"
#include "rzg2l_du_kms.h"

/* -----------------------------------------------------------------------------
 * Device Information
 */

static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = {
	.channels_mask = BIT(0),
	.routes = {
		[RZG2L_DU_OUTPUT_DPAD0] = {
			.possible_outputs = BIT(0),
			.port = 0,
		},
	},
	.mode_clock_min = 20875,
	.mode_clock_max = 83500,
};

static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
	.channels_mask = BIT(0),
	.routes = {
		[RZG2L_DU_OUTPUT_DSI0] = {
			.possible_outputs = BIT(0),
			.port = 0,
		},
		[RZG2L_DU_OUTPUT_DPAD0] = {
			.possible_outputs = BIT(0),
			.port = 1,
		}
	},
	.mode_clock_min = 20875,
	.mode_clock_max = 83500,
};

static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = {
	.channels_mask = BIT(0),
	.routes = {
		[RZG2L_DU_OUTPUT_DSI0] = {
			.possible_outputs = BIT(0),
			.port = 0,
		},
	},
};

static const struct rzg2l_du_device_info rzg2l_du_r9a09g077_info = {
	.channels_mask = BIT(0),
	.routes = {
		[RZG2L_DU_OUTPUT_DPAD0] = {
			.possible_outputs = BIT(0),
			.port = 0,
		},
	},
	.features = RZG2L_DU_FEATURE_DPIO_OE,
	.mode_clock_min = 5000,
	.mode_clock_max = 100000,
};

static const struct of_device_id rzg2l_du_of_table[] = {
	{ .compatible = "renesas,r9a07g043u-du", .data = &rzg2l_du_r9a07g043u_info },
	{ .compatible = "renesas,r9a07g044-du", .data = &rzg2l_du_r9a07g044_info },
	{ .compatible = "renesas,r9a09g057-du", .data = &rzg2l_du_r9a09g057_info },
	{ .compatible = "renesas,r9a09g077-du", .data = &rzg2l_du_r9a09g077_info },
	{ /* sentinel */ }
};

MODULE_DEVICE_TABLE(of, rzg2l_du_of_table);

Annotation

Implementation Notes